[people/ms/u-boot.git] / include / configs / mx35pdk.h

/*
 * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * Configuration for the MX35pdk Freescale board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_MX35

#define CONFIG_SYS_FSL_CLK

/* Set TEXT at the beginning of the NOR flash */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/*
 * PMIC Configs
 */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x08
#define CONFIG_RTC_MC13XXX

/*
 * MFD MC9SDZ60
 */
#define CONFIG_FSL_MC9SDZ60
#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR	0x69

/*
 * UART (console)
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1

/*
 * Command definition
 */

#define CONFIG_NET_RETRY_COUNT	100


#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

/*
 * Ethernet on the debug board (SMC911)
 */
#define CONFIG_HAS_ETH1
#define CONFIG_ETHPRIME

/*
 * Ethernet on SOC (FEC)
 */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1F

#define CONFIG_MII

#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
#define PHYS_SDRAM_2		CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * MTD Command for mtdparts
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				CONFIG_SYS_MONITOR_LEN)

#if defined(CONFIG_FSL_ENV_IN_NAND)
	#define CONFIG_ENV_OFFSET       (1024 * 1024)
#endif

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER

/* A non-standard buffered write algorithm */
#define CONFIG_FLASH_SPANSION_S29WS_N
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * NAND FLASH driver setup
 */
#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

/* EHCI driver */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
#define CONFIG_MXC_USB_PORT	0
#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
				 MXC_EHCI_POWER_PINS_ENABLED | \
				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)

/* mmc driver */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*
 * Default environment and default scripts
 * to update uboot and load kernel
 */

#define CONFIG_HOSTNAME "mx35pdk"
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth1\0"							\
	"ethprime=smc911x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=80800000\0"						\
	"kernel_addr_r=80800000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
	"update=protect off ${uboot_addr} +80000;"			\
		"erase ${uboot_addr} +80000;"				\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"bootcmd=run net_nfs\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
eae4988b SB	1	/*
	2	* (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
	6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	7	*
	8	* Configuration for the MX35pdk Freescale board.
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
eae4988b SB	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	#include <asm/arch/imx-regs.h>
	17
	18	/* High Level Configuration Options */
eae4988b	19	#define CONFIG_MX35
eae4988b	20
18fb0e3c	21	#define CONFIG_SYS_FSL_CLK
eae4988b SB	22
eae4988b SB	23	/* Set TEXT at the beginning of the NOR flash */
eae4988b	24
eae4988b SB	25	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	26	#define CONFIG_REVISION_TAG
	27	#define CONFIG_SETUP_MEMORY_TAGS
	28	#define CONFIG_INITRD_TAG
	29
	30	/*
	31	* Size of malloc() pool
	32	*/
	33	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	34
	35	/*
	36	* Hardware drivers
	37	*/
b089d039	38	#define CONFIG_SYS_I2C
b089d039	39	#define CONFIG_SYS_I2C_MXC
03544c66 AA	40	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	41	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	42	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
eae4988b	43
eae4988b SB	44	/*
	45	* PMIC Configs
	46	*/
be3b51aa ŁM	47	#define CONFIG_POWER
	48	#define CONFIG_POWER_I2C
	49	#define CONFIG_POWER_FSL
913702ca	50	#define CONFIG_POWER_FSL_MC13892
eae4988b	51	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
d28d6a96	52	#define CONFIG_RTC_MC13XXX
eae4988b SB	53
	54	/*
	55	* MFD MC9SDZ60
	56	*/
	57	#define CONFIG_FSL_MC9SDZ60
	58	#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
	59
	60	/*
	61	* UART (console)
	62	*/
	63	#define CONFIG_MXC_UART
40f6fffe	64	#define CONFIG_MXC_UART_BASE UART1_BASE
eae4988b SB	65
	66	/* allow to overwrite serial and ethaddr */
	67	#define CONFIG_ENV_OVERWRITE
	68	#define CONFIG_CONS_INDEX 1
eae4988b SB	69
	70	/*
	71	* Command definition
	72	*/
eae4988b	73
eae4988b SB	74	#define CONFIG_NET_RETRY_COUNT 100
eae4988b SB	75
eae4988b SB	76
	77	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	78
	79	/*
	80	* Ethernet on the debug board (SMC911)
	81	*/
eae4988b	82	#define CONFIG_HAS_ETH1
eae4988b SB	83	#define CONFIG_ETHPRIME
	84
	85	/*
	86	* Ethernet on SOC (FEC)
	87	*/
	88	#define CONFIG_FEC_MXC
	89	#define IMX_FEC_BASE FEC_BASE_ADDR
	90	#define CONFIG_FEC_MXC_PHYADDR 0x1F
	91
	92	#define CONFIG_MII
eae4988b SB	93
	94	#define CONFIG_ARP_TIMEOUT 200UL
	95
	96	/*
	97	* Miscellaneous configurable options
	98	*/
eae4988b SB	99
	100	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
	101	#define CONFIG_SYS_MEMTEST_END 0x10000
	102
eae4988b SB	103	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
eae4988b SB	104
eae4988b SB	105	/*
	106	* Physical Memory Map
	107	*/
6b5acfc1	108	#define CONFIG_NR_DRAM_BANKS 2
eae4988b SB	109	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
eae4988b SB	110	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
6b5acfc1 SB	111	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
6b5acfc1 SB	112	#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
eae4988b SB	113
	114	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
	115	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
	116	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
	117	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	118	GENERATED_GBL_DATA_SIZE)
	119	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	120	CONFIG_SYS_GBL_DATA_OFFSET)
	121
	122	/*
	123	* MTD Command for mtdparts
	124	*/
eae4988b SB	125	#define CONFIG_MTD_DEVICE
	126	#define CONFIG_FLASH_CFI_MTD
	127	#define CONFIG_MTD_PARTITIONS
eae4988b SB	128
	129	/*
	130	* FLASH and environment organization
	131	*/
	132	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
	133	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	134	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	135	/* Monitor at beginning of flash */
	136	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	137	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	138
	139	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	140	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	141
	142	/* Address and size of Redundant Environment Sector */
	143	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	144	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	145
	146	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	147	CONFIG_SYS_MONITOR_LEN)
	148
eae4988b	149	#if defined(CONFIG_FSL_ENV_IN_NAND)
eae4988b SB	150	#define CONFIG_ENV_OFFSET (1024 * 1024)
	151	#endif
	152
	153	/*
	154	* CFI FLASH driver setup
	155	*/
	156	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
	157	#define CONFIG_FLASH_CFI_DRIVER
	158
	159	/* A non-standard buffered write algorithm */
	160	#define CONFIG_FLASH_SPANSION_S29WS_N
	161	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
	162	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
	163
	164	/*
	165	* NAND FLASH driver setup
	166	*/
eae4988b SB	167	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
	168	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	169	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
	170	#define CONFIG_MXC_NAND_HWECC
	171	#define CONFIG_SYS_NAND_LARGEPAGE
	172
961a7628	173	/* EHCI driver */
961a7628 BT	174	#define CONFIG_EHCI_IS_TDI
	175	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	176	#define CONFIG_USB_EHCI_MXC
	177	#define CONFIG_MXC_USB_PORT 0
	178	#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI \| \
	179	MXC_EHCI_POWER_PINS_ENABLED \| \
	180	MXC_EHCI_OC_PIN_ACTIVE_LOW)
	181	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT \| MXC_EHCI_MODE_UTMI)
	182
3292539e	183	/* mmc driver */
3292539e SB	184	#define CONFIG_FSL_ESDHC
	185	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	186	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	187
eae4988b SB	188	/*
	189	* Default environment and default scripts
	190	* to update uboot and load kernel
	191	*/
eae4988b SB	192
	193	#define CONFIG_HOSTNAME "mx35pdk"
	194	#define CONFIG_EXTRA_ENV_SETTINGS \
	195	"netdev=eth1\0" \
	196	"ethprime=smc911x\0" \
	197	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	198	"nfsroot=${serverip}:${rootpath}\0" \
	199	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	200	"addip_sta=setenv bootargs ${bootargs} " \
	201	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	202	":${hostname}:${netdev}:off panic=1\0" \
	203	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	204	"addip=if test -n ${ipdyn};then run addip_dyn;" \
93ea89f0	205	"else run addip_sta;fi\0" \
eae4988b SB	206	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	207	"addtty=setenv bootargs ${bootargs}" \
	208	" console=ttymxc0,${baudrate}\0" \
	209	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	210	"loadaddr=80800000\0" \
	211	"kernel_addr_r=80800000\0" \
93ea89f0 MV	212	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
	213	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
	214	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
eae4988b SB	215	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	216	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	217	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	218	"bootm ${kernel_addr}\0" \
	219	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	220	"run nfsargs addip addtty addmtd addmisc;" \
	221	"bootm ${kernel_addr_r}\0" \
	222	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
	223	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
93ea89f0	224	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
eae4988b	225	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0	226	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
3292539e SB	227	"update=protect off ${uboot_addr} +80000;" \
3292539e SB	228	"erase ${uboot_addr} +80000;" \
eae4988b SB	229	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
	230	"upd=if run load;then echo Updating u-boot;if run update;" \
	231	"then echo U-Boot updated;" \
	232	"else echo Error updating u-boot !;" \
	233	"echo Board without bootloader !!;" \
	234	"fi;" \
	235	"else echo U-Boot not downloaded..exiting;fi\0" \
	236	"bootcmd=run net_nfs\0"
	237
	238	#endif /* __CONFIG_H */