[people/ms/u-boot.git] / include / configs / mx53evk.h

/*
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the MX53-EVK Freescale board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_EVK

#include <asm/arch/imx-regs.h>

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

#define CONFIG_SYS_FSL_CLK

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* PMIC Configs */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR    8
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_RTC_MC13XXX

/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	2

/* Eth Configs */
#define CONFIG_MII

#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1F

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX		1

/* Command definition */

#define CONFIG_ETHPRIME		"FEC0"

#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"script=boot.scr\0" \
	"uimage=uImage\0" \
	"mmcdev=0\0" \
	"mmcpart=2\0" \
	"mmcroot=/dev/mmcblk0p3 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"loadbootscript=" \
		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm\0" \
	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
		"root=/dev/nfs " \
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	"netboot=echo Booting from net ...; " \
		"run netargs; " \
		"dhcp ${uimage}; bootm\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run netboot; " \
			"fi; " \
		"fi; " \
	"else run netboot; fi"

#define CONFIG_ARP_TIMEOUT	200UL

/* Miscellaneous configurable options */

#define CONFIG_SYS_MEMTEST_START       0x70000000
#define CONFIG_SYS_MEMTEST_END         0x70010000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
#define CONFIG_ENV_SIZE        (8 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0

#endif				/* __CONFIG_H */
Commit	Line	Data
94391fbc LHR	1	/*
	2	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	3	*
	4	* Configuration settings for the MX53-EVK Freescale board.
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
94391fbc LHR	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
00e11a43 FE	12	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
00e11a43 FE	13
94391fbc LHR	14	#include <asm/arch/imx-regs.h>
94391fbc LHR	15
a7abca01	16	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
a7abca01 FE	17	#define CONFIG_SETUP_MEMORY_TAGS
a7abca01 FE	18	#define CONFIG_INITRD_TAG
fd622f23	19	#define CONFIG_REVISION_TAG
94391fbc	20
18fb0e3c	21	#define CONFIG_SYS_FSL_CLK
851f556a	22
94391fbc LHR	23	/* Size of malloc() pool */
	24	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
	25
94391fbc	26	#define CONFIG_MXC_UART
40f6fffe	27	#define CONFIG_MXC_UART_BASE UART1_BASE
94391fbc LHR	28
94391fbc LHR	29	/* I2C Configs */
b089d039	30	#define CONFIG_SYS_I2C
b089d039	31	#define CONFIG_SYS_I2C_MXC
03544c66 AA	32	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	33	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	34	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
94391fbc LHR	35
94391fbc LHR	36	/* PMIC Configs */
be3b51aa ŁM	37	#define CONFIG_POWER
	38	#define CONFIG_POWER_I2C
	39	#define CONFIG_POWER_FSL
94391fbc	40	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
913702ca	41	#define CONFIG_POWER_FSL_MC13892
4f97c88e	42	#define CONFIG_RTC_MC13XXX
94391fbc LHR	43
	44	/* MMC Configs */
	45	#define CONFIG_FSL_ESDHC
	46	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	47	#define CONFIG_SYS_FSL_ESDHC_NUM 2
	48
94391fbc	49	/* Eth Configs */
94391fbc	50	#define CONFIG_MII
94391fbc LHR	51
	52	#define CONFIG_FEC_MXC
	53	#define IMX_FEC_BASE FEC_BASE_ADDR
	54	#define CONFIG_FEC_MXC_PHYADDR 0x1F
	55
94391fbc LHR	56	/* allow to overwrite serial and ethaddr */
	57	#define CONFIG_ENV_OVERWRITE
	58	#define CONFIG_CONS_INDEX 1
94391fbc LHR	59
94391fbc LHR	60	/* Command definition */
94391fbc	61
28b119e9	62	#define CONFIG_ETHPRIME "FEC0"
94391fbc LHR	63
94391fbc LHR	64	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
94391fbc LHR	65
	66	#define CONFIG_EXTRA_ENV_SETTINGS \
	67	"script=boot.scr\0" \
	68	"uimage=uImage\0" \
	69	"mmcdev=0\0" \
	70	"mmcpart=2\0" \
	71	"mmcroot=/dev/mmcblk0p3 rw\0" \
	72	"mmcrootfstype=ext3 rootwait\0" \
	73	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
	74	"root=${mmcroot} " \
	75	"rootfstype=${mmcrootfstype}\0" \
	76	"loadbootscript=" \
	77	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	78	"bootscript=echo Running bootscript from mmc ...; " \
	79	"source\0" \
	80	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
	81	"mmcboot=echo Booting from mmc ...; " \
	82	"run mmcargs; " \
	83	"bootm\0" \
	84	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
	85	"root=/dev/nfs " \
	86	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	87	"netboot=echo Booting from net ...; " \
	88	"run netargs; " \
	89	"dhcp ${uimage}; bootm\0" \
	90
	91	#define CONFIG_BOOTCOMMAND \
66968110	92	"mmc dev ${mmcdev}; if mmc rescan; then " \
94391fbc LHR	93	"if run loadbootscript; then " \
	94	"run bootscript; " \
	95	"else " \
	96	"if run loaduimage; then " \
	97	"run mmcboot; " \
	98	"else run netboot; " \
	99	"fi; " \
	100	"fi; " \
	101	"else run netboot; fi"
	102
	103	#define CONFIG_ARP_TIMEOUT 200UL
	104
	105	/* Miscellaneous configurable options */
94391fbc	106
94391fbc	107	#define CONFIG_SYS_MEMTEST_START 0x70000000
bc9d5ef1	108	#define CONFIG_SYS_MEMTEST_END 0x70010000
94391fbc LHR	109
	110	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	111
94391fbc LHR	112	/* Physical Memory Map */
	113	#define CONFIG_NR_DRAM_BANKS 1
	114	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	115	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
	116
	117	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
	118	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
	119	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
	120
	121	#define CONFIG_SYS_INIT_SP_OFFSET \
	122	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	123	#define CONFIG_SYS_INIT_SP_ADDR \
	124	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	125
e856bdcf	126	/* environment organization */
94391fbc LHR	127	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
94391fbc LHR	128	#define CONFIG_ENV_SIZE (8 * 1024)
94391fbc LHR	129	#define CONFIG_SYS_MMC_ENV_DEV 0
	130
	131	#endif /* __CONFIG_H */