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94391fbc LHR |
1 | /* |
2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the MX53-EVK Freescale board. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
25 | #define CONFIG_MX53 | |
26 | ||
27 | #define CONFIG_SYS_MX5_HCLK 24000000 | |
28 | #define CONFIG_SYS_MX5_CLK32 32768 | |
29 | #define CONFIG_DISPLAY_CPUINFO | |
30 | #define CONFIG_DISPLAY_BOARDINFO | |
31 | ||
00e11a43 FE |
32 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK |
33 | ||
94391fbc LHR |
34 | #include <asm/arch/imx-regs.h> |
35 | ||
a7abca01 | 36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
a7abca01 FE |
37 | #define CONFIG_SETUP_MEMORY_TAGS |
38 | #define CONFIG_INITRD_TAG | |
94391fbc | 39 | |
a7abca01 | 40 | #define CONFIG_OF_LIBFDT |
2fa8ca98 | 41 | |
94391fbc LHR |
42 | /* Size of malloc() pool */ |
43 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
44 | ||
45 | #define CONFIG_BOARD_EARLY_INIT_F | |
9660e442 | 46 | #define CONFIG_BOARD_LATE_INIT |
94391fbc LHR |
47 | #define CONFIG_MXC_GPIO |
48 | ||
49 | #define CONFIG_MXC_UART | |
40f6fffe | 50 | #define CONFIG_MXC_UART_BASE UART1_BASE |
94391fbc LHR |
51 | |
52 | /* I2C Configs */ | |
a7abca01 FE |
53 | #define CONFIG_CMD_I2C |
54 | #define CONFIG_HARD_I2C | |
55 | #define CONFIG_I2C_MXC | |
de6f604d | 56 | #define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR |
94391fbc | 57 | #define CONFIG_SYS_I2C_SPEED 100000 |
94391fbc LHR |
58 | |
59 | /* PMIC Configs */ | |
bba1b6cf SB |
60 | #define CONFIG_PMIC |
61 | #define CONFIG_PMIC_I2C | |
62 | #define CONFIG_PMIC_FSL | |
94391fbc | 63 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 |
4f97c88e | 64 | #define CONFIG_RTC_MC13XXX |
94391fbc LHR |
65 | |
66 | /* MMC Configs */ | |
67 | #define CONFIG_FSL_ESDHC | |
68 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
69 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
70 | ||
71 | #define CONFIG_MMC | |
72 | #define CONFIG_CMD_MMC | |
73 | #define CONFIG_GENERIC_MMC | |
74 | #define CONFIG_CMD_FAT | |
75 | #define CONFIG_DOS_PARTITION | |
76 | ||
77 | /* Eth Configs */ | |
78 | #define CONFIG_HAS_ETH1 | |
94391fbc | 79 | #define CONFIG_MII |
94391fbc LHR |
80 | |
81 | #define CONFIG_FEC_MXC | |
82 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
83 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
84 | ||
85 | #define CONFIG_CMD_PING | |
86 | #define CONFIG_CMD_DHCP | |
87 | #define CONFIG_CMD_MII | |
88 | #define CONFIG_CMD_NET | |
4f97c88e | 89 | #define CONFIG_CMD_DATE |
94391fbc LHR |
90 | |
91 | /* allow to overwrite serial and ethaddr */ | |
92 | #define CONFIG_ENV_OVERWRITE | |
93 | #define CONFIG_CONS_INDEX 1 | |
94 | #define CONFIG_BAUDRATE 115200 | |
94391fbc LHR |
95 | |
96 | /* Command definition */ | |
97 | #include <config_cmd_default.h> | |
98 | ||
99 | #undef CONFIG_CMD_IMLS | |
100 | ||
101 | #define CONFIG_BOOTDELAY 3 | |
102 | ||
28b119e9 | 103 | #define CONFIG_ETHPRIME "FEC0" |
94391fbc LHR |
104 | |
105 | #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ | |
106 | #define CONFIG_SYS_TEXT_BASE 0x77800000 | |
107 | ||
108 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
109 | "script=boot.scr\0" \ | |
110 | "uimage=uImage\0" \ | |
111 | "mmcdev=0\0" \ | |
112 | "mmcpart=2\0" \ | |
113 | "mmcroot=/dev/mmcblk0p3 rw\0" \ | |
114 | "mmcrootfstype=ext3 rootwait\0" \ | |
115 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
116 | "root=${mmcroot} " \ | |
117 | "rootfstype=${mmcrootfstype}\0" \ | |
118 | "loadbootscript=" \ | |
119 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
120 | "bootscript=echo Running bootscript from mmc ...; " \ | |
121 | "source\0" \ | |
122 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ | |
123 | "mmcboot=echo Booting from mmc ...; " \ | |
124 | "run mmcargs; " \ | |
125 | "bootm\0" \ | |
126 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
127 | "root=/dev/nfs " \ | |
128 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
129 | "netboot=echo Booting from net ...; " \ | |
130 | "run netargs; " \ | |
131 | "dhcp ${uimage}; bootm\0" \ | |
132 | ||
133 | #define CONFIG_BOOTCOMMAND \ | |
134 | "if mmc rescan ${mmcdev}; then " \ | |
135 | "if run loadbootscript; then " \ | |
136 | "run bootscript; " \ | |
137 | "else " \ | |
138 | "if run loaduimage; then " \ | |
139 | "run mmcboot; " \ | |
140 | "else run netboot; " \ | |
141 | "fi; " \ | |
142 | "fi; " \ | |
143 | "else run netboot; fi" | |
144 | ||
145 | #define CONFIG_ARP_TIMEOUT 200UL | |
146 | ||
147 | /* Miscellaneous configurable options */ | |
148 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
149 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
94391fbc LHR |
150 | #define CONFIG_SYS_PROMPT "MX53EVK U-Boot > " |
151 | #define CONFIG_AUTO_COMPLETE | |
152 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
153 | ||
154 | /* Print Buffer Size */ | |
155 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
156 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
157 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
158 | ||
159 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
bc9d5ef1 | 160 | #define CONFIG_SYS_MEMTEST_END 0x70010000 |
94391fbc LHR |
161 | |
162 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
163 | ||
164 | #define CONFIG_SYS_HZ 1000 | |
165 | #define CONFIG_CMDLINE_EDITING | |
166 | ||
94391fbc LHR |
167 | /* Physical Memory Map */ |
168 | #define CONFIG_NR_DRAM_BANKS 1 | |
169 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
170 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) | |
171 | ||
172 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
173 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
174 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
175 | ||
176 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
177 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
178 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
179 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
180 | ||
181 | /* FLASH and environment organization */ | |
182 | #define CONFIG_SYS_NO_FLASH | |
183 | ||
184 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
185 | #define CONFIG_ENV_SIZE (8 * 1024) | |
186 | #define CONFIG_ENV_IS_IN_MMC | |
187 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
188 | ||
189 | #endif /* __CONFIG_H */ |