[people/ms/u-boot.git] / include / configs / mx53loco.h

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 * Jason Liu <r64343@freescale.com>
 *
 * Configuration settings for Freescale MX53 low cost board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MX53

#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO

#include <asm/arch/imx-regs.h>

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_SYS_FSL_CLK

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	2

#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION

/* Eth Configs */
#define CONFIG_MII

#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1F

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII

/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT	1
#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS	0

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX		1
#define CONFIG_BAUDRATE			115200

/* Command definition */
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_BOOTDELAY	1

#define CONFIG_ETHPRIME		"FEC0"

#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE    0x77800000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"script=boot.scr\0" \
	"image=zImage\0" \
	"fdt_addr=0x71000000\0" \
	"boot_fdt=try\0" \
	"ip_dyn=yes\0" \
	"mmcdev=0\0" \
	"mmcpart=1\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
	"loadbootscript=" \
		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
			"if run loadfdt; then " \
				"bootz ${loadaddr} - ${fdt_addr}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo WARN: Cannot load the DT; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0" \
	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
		"root=/dev/nfs " \
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	"netboot=echo Booting from net ...; " \
		"run netargs; " \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"${get_cmd} ${image}; " \
		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
				"bootz ${loadaddr} - ${fdt_addr}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo ERROR: Cannot load the DT; " \
					"exit; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0"

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loadimage; then " \
				"run mmcboot; " \
			"else run netboot; " \
			"fi; " \
		"fi; " \
	"else run netboot; fi"

#define CONFIG_ARP_TIMEOUT	200UL

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START       0x70000000
#define CONFIG_SYS_MEMTEST_END         0x70010000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS	2
#define PHYS_SDRAM_1			CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2			CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE			(gd->ram_size)

#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH

#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
#define CONFIG_ENV_SIZE        (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0

#define CONFIG_CMD_SATA
#ifdef CONFIG_CMD_SATA
	#define CONFIG_DWC_AHSATA
	#define CONFIG_SYS_SATA_MAX_DEVICE      1
	#define CONFIG_DWC_AHSATA_PORT_ID       0
	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
	#define CONFIG_LBA48
	#define CONFIG_LIBATA
#endif

/* Framebuffer and LCD */
#define CONFIG_PREBOOT
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK	200000000

#endif				/* __CONFIG_H */
Commit	Line	Data
938080dc JL	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	* Jason Liu <r64343@freescale.com>
	4	*
	5	* Configuration settings for Freescale MX53 low cost board.
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
938080dc JL	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#define CONFIG_MX53
	14
938080dc JL	15	#define CONFIG_DISPLAY_BOARDINFO
938080dc JL	16
9df82896 FE	17	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
9df82896 FE	18
938080dc JL	19	#include <asm/arch/imx-regs.h>
	20
	21	#define CONFIG_CMDLINE_TAG
938080dc JL	22	#define CONFIG_SETUP_MEMORY_TAGS
	23	#define CONFIG_INITRD_TAG
	24
18fb0e3c	25	#define CONFIG_SYS_FSL_CLK
6ca896f9	26
938080dc	27	/* Size of malloc() pool */
f714b0a9	28	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
938080dc JL	29
938080dc JL	30	#define CONFIG_BOARD_EARLY_INIT_F
54bb8411	31	#define CONFIG_BOARD_LATE_INIT
938080dc	32	#define CONFIG_MXC_GPIO
54cd1dee	33	#define CONFIG_REVISION_TAG
938080dc JL	34
938080dc JL	35	#define CONFIG_MXC_UART
40f6fffe	36	#define CONFIG_MXC_UART_BASE UART1_BASE
938080dc JL	37
	38	/* MMC Configs */
	39	#define CONFIG_FSL_ESDHC
	40	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	41	#define CONFIG_SYS_FSL_ESDHC_NUM 2
	42
	43	#define CONFIG_MMC
	44	#define CONFIG_CMD_MMC
	45	#define CONFIG_GENERIC_MMC
54e0f96f	46	#define CONFIG_CMD_FS_GENERIC
938080dc	47	#define CONFIG_CMD_FAT
f92e4e6c	48	#define CONFIG_CMD_EXT2
938080dc JL	49	#define CONFIG_DOS_PARTITION
	50
	51	/* Eth Configs */
938080dc	52	#define CONFIG_MII
938080dc JL	53
	54	#define CONFIG_FEC_MXC
	55	#define IMX_FEC_BASE FEC_BASE_ADDR
	56	#define CONFIG_FEC_MXC_PHYADDR 0x1F
	57
	58	#define CONFIG_CMD_PING
	59	#define CONFIG_CMD_DHCP
	60	#define CONFIG_CMD_MII
938080dc	61
45cf6ada WG	62	/* USB Configs */
	63	#define CONFIG_CMD_USB
	64	#define CONFIG_CMD_FAT
	65	#define CONFIG_USB_EHCI
	66	#define CONFIG_USB_EHCI_MX5
	67	#define CONFIG_USB_STORAGE
	68	#define CONFIG_USB_HOST_ETHER
	69	#define CONFIG_USB_ETHER_ASIX
a743415f	70	#define CONFIG_USB_ETHER_MCS7830
45cf6ada WG	71	#define CONFIG_USB_ETHER_SMSC95XX
	72	#define CONFIG_MXC_USB_PORT 1
	73	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	74	#define CONFIG_MXC_USB_FLAGS 0
	75
e7e33722	76	/* I2C Configs */
b089d039	77	#define CONFIG_SYS_I2C
b089d039	78	#define CONFIG_SYS_I2C_MXC
03544c66 AA	79	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	80	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	81	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
e7e33722 FE	82
e7e33722 FE	83	/* PMIC Controller */
be3b51aa ŁM	84	#define CONFIG_POWER
be3b51aa ŁM	85	#define CONFIG_POWER_I2C
2988e866	86	#define CONFIG_DIALOG_POWER
be3b51aa	87	#define CONFIG_POWER_FSL
913702ca	88	#define CONFIG_POWER_FSL_MC13892
e7e33722	89	#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
5b547f3c	90	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
e7e33722	91
938080dc JL	92	/* allow to overwrite serial and ethaddr */
	93	#define CONFIG_ENV_OVERWRITE
	94	#define CONFIG_CONS_INDEX 1
	95	#define CONFIG_BAUDRATE 115200
938080dc JL	96
938080dc JL	97	/* Command definition */
c14ab2ae	98	#define CONFIG_CMD_BOOTZ
ec62c07a	99	#define CONFIG_SUPPORT_RAW_INITRD
938080dc	100
fbae0d10	101	#define CONFIG_BOOTDELAY 1
938080dc	102
28b119e9	103	#define CONFIG_ETHPRIME "FEC0"
938080dc	104
fe51f787	105	#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
938080dc JL	106	#define CONFIG_SYS_TEXT_BASE 0x77800000
	107
	108	#define CONFIG_EXTRA_ENV_SETTINGS \
	109	"script=boot.scr\0" \
f28154b5	110	"image=zImage\0" \
e0df5353 OS	111	"fdt_addr=0x71000000\0" \
	112	"boot_fdt=try\0" \
	113	"ip_dyn=yes\0" \
938080dc	114	"mmcdev=0\0" \
254fd8da OS	115	"mmcpart=1\0" \
254fd8da OS	116	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
e0df5353	117	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
938080dc	118	"loadbootscript=" \
54e0f96f	119	"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
938080dc JL	120	"bootscript=echo Running bootscript from mmc ...; " \
938080dc JL	121	"source\0" \
54e0f96f GG	122	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
54e0f96f GG	123	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
938080dc JL	124	"mmcboot=echo Booting from mmc ...; " \
938080dc JL	125	"run mmcargs; " \
e0df5353 OS	126	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
e0df5353 OS	127	"if run loadfdt; then " \
f28154b5	128	"bootz ${loadaddr} - ${fdt_addr}; " \
e0df5353 OS	129	"else " \
e0df5353 OS	130	"if test ${boot_fdt} = try; then " \
f28154b5	131	"bootz; " \
e0df5353 OS	132	"else " \
	133	"echo WARN: Cannot load the DT; " \
	134	"fi; " \
	135	"fi; " \
	136	"else " \
f28154b5	137	"bootz; " \
e0df5353	138	"fi;\0" \
938080dc JL	139	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
	140	"root=/dev/nfs " \
	141	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	142	"netboot=echo Booting from net ...; " \
	143	"run netargs; " \
e0df5353 OS	144	"if test ${ip_dyn} = yes; then " \
	145	"setenv get_cmd dhcp; " \
	146	"else " \
	147	"setenv get_cmd tftp; " \
	148	"fi; " \
f28154b5	149	"${get_cmd} ${image}; " \
e0df5353 OS	150	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
e0df5353 OS	151	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
f28154b5	152	"bootz ${loadaddr} - ${fdt_addr}; " \
e0df5353 OS	153	"else " \
e0df5353 OS	154	"if test ${boot_fdt} = try; then " \
f28154b5	155	"bootz; " \
e0df5353 OS	156	"else " \
	157	"echo ERROR: Cannot load the DT; " \
	158	"exit; " \
	159	"fi; " \
	160	"fi; " \
	161	"else " \
f28154b5	162	"bootz; " \
e0df5353	163	"fi;\0"
938080dc JL	164
938080dc JL	165	#define CONFIG_BOOTCOMMAND \
66968110	166	"mmc dev ${mmcdev}; if mmc rescan; then " \
938080dc JL	167	"if run loadbootscript; then " \
	168	"run bootscript; " \
	169	"else " \
f28154b5	170	"if run loadimage; then " \
938080dc JL	171	"run mmcboot; " \
	172	"else run netboot; " \
	173	"fi; " \
	174	"fi; " \
	175	"else run netboot; fi"
	176
	177	#define CONFIG_ARP_TIMEOUT 200UL
	178
	179	/* Miscellaneous configurable options */
	180	#define CONFIG_SYS_LONGHELP /* undef to save memory */
938080dc	181	#define CONFIG_AUTO_COMPLETE
e0df5353	182	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
938080dc	183
938080dc JL	184	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	185	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	186
	187	#define CONFIG_SYS_MEMTEST_START 0x70000000
	188	#define CONFIG_SYS_MEMTEST_END 0x70010000
	189
	190	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	191
938080dc JL	192	#define CONFIG_CMDLINE_EDITING
938080dc JL	193
938080dc JL	194	/* Physical Memory Map */
938080dc JL	195	#define CONFIG_NR_DRAM_BANKS 2
31c832f9 MV	196	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	197	#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
	198	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
	199	#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
	200	#define PHYS_SDRAM_SIZE (gd->ram_size)
938080dc JL	201
	202	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
	203	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
	204	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
	205
	206	#define CONFIG_SYS_INIT_SP_OFFSET \
	207	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	208	#define CONFIG_SYS_INIT_SP_ADDR \
	209	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	210
	211	/* FLASH and environment organization */
	212	#define CONFIG_SYS_NO_FLASH
	213
	214	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
	215	#define CONFIG_ENV_SIZE (8 * 1024)
	216	#define CONFIG_ENV_IS_IN_MMC
	217	#define CONFIG_SYS_MMC_ENV_DEV 0
	218
f92e4e6c SB	219	#define CONFIG_CMD_SATA
	220	#ifdef CONFIG_CMD_SATA
	221	#define CONFIG_DWC_AHSATA
	222	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	223	#define CONFIG_DWC_AHSATA_PORT_ID 0
	224	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
	225	#define CONFIG_LBA48
	226	#define CONFIG_LIBATA
	227	#endif
	228
f714b0a9 FE	229	/* Framebuffer and LCD */
	230	#define CONFIG_PREBOOT
	231	#define CONFIG_VIDEO
695af9ab	232	#define CONFIG_VIDEO_IPUV3
f714b0a9 FE	233	#define CONFIG_CFB_CONSOLE
f714b0a9 FE	234	#define CONFIG_VGA_AS_SINGLE_DEVICE
3e077370 SB	235	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
3e077370 SB	236	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
f714b0a9 FE	237	#define CONFIG_VIDEO_BMP_RLE8
	238	#define CONFIG_SPLASH_SCREEN
	239	#define CONFIG_BMP_16BPP
	240	#define CONFIG_VIDEO_LOGO
c606608a	241	#define CONFIG_IPUV3_CLK 200000000
f714b0a9	242
938080dc	243	#endif /* __CONFIG_H */