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1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
c4c596fb 4 * Configuration settings for the MX53SMD Freescale board.
860b32ee 5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#define CONFIG_MX53
13
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14#define CONFIG_DISPLAY_CPUINFO
15#define CONFIG_DISPLAY_BOARDINFO
16
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17#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
18
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19#include <asm/arch/imx-regs.h>
20
21#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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22#define CONFIG_SETUP_MEMORY_TAGS
23#define CONFIG_INITRD_TAG
fd622f23 24#define CONFIG_REVISION_TAG
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25
26/* Size of malloc() pool */
27#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
28
29#define CONFIG_BOARD_EARLY_INIT_F
30#define CONFIG_MXC_GPIO
31
32#define CONFIG_MXC_UART
40f6fffe 33#define CONFIG_MXC_UART_BASE UART1_BASE
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34
35/* I2C Configs */
36#define CONFIG_CMD_I2C
37#define CONFIG_HARD_I2C
38#define CONFIG_I2C_MXC
de6f604d 39#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
860b32ee 40#define CONFIG_SYS_I2C_SPEED 100000
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41
42/* MMC Configs */
43#define CONFIG_FSL_ESDHC
44#define CONFIG_SYS_FSL_ESDHC_ADDR 0
45#define CONFIG_SYS_FSL_ESDHC_NUM 1
46
47#define CONFIG_MMC
48#define CONFIG_CMD_MMC
49#define CONFIG_GENERIC_MMC
50#define CONFIG_CMD_FAT
51#define CONFIG_DOS_PARTITION
52
53/* Eth Configs */
54#define CONFIG_HAS_ETH1
860b32ee 55#define CONFIG_MII
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56
57#define CONFIG_FEC_MXC
58#define IMX_FEC_BASE FEC_BASE_ADDR
59#define CONFIG_FEC_MXC_PHYADDR 0x1F
60
61#define CONFIG_CMD_PING
62#define CONFIG_CMD_DHCP
63#define CONFIG_CMD_MII
64#define CONFIG_CMD_NET
65
66/* allow to overwrite serial and ethaddr */
67#define CONFIG_ENV_OVERWRITE
68#define CONFIG_CONS_INDEX 1
69#define CONFIG_BAUDRATE 115200
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70
71/* Command definition */
72#include <config_cmd_default.h>
73
74#undef CONFIG_CMD_IMLS
75
76#define CONFIG_BOOTDELAY 3
77
28b119e9 78#define CONFIG_ETHPRIME "FEC0"
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79
80#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
81#define CONFIG_SYS_TEXT_BASE 0x77800000
82
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 "script=boot.scr\0" \
85 "uimage=uImage\0" \
86 "mmcdev=0\0" \
87 "mmcpart=2\0" \
88 "mmcroot=/dev/mmcblk0p3 rw\0" \
89 "mmcrootfstype=ext3 rootwait\0" \
90 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
91 "root=${mmcroot} " \
92 "rootfstype=${mmcrootfstype}\0" \
93 "loadbootscript=" \
94 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
95 "bootscript=echo Running bootscript from mmc ...; " \
96 "source\0" \
97 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
98 "mmcboot=echo Booting from mmc ...; " \
99 "run mmcargs; " \
100 "bootm\0" \
101 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
102 "root=/dev/nfs " \
103 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
104 "netboot=echo Booting from net ...; " \
105 "run netargs; " \
106 "dhcp ${uimage}; bootm\0" \
107
108#define CONFIG_BOOTCOMMAND \
66968110 109 "mmc dev ${mmcdev}; if mmc rescan; then " \
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110 "if run loadbootscript; then " \
111 "run bootscript; " \
112 "else " \
113 "if run loaduimage; then " \
114 "run mmcboot; " \
115 "else run netboot; " \
116 "fi; " \
117 "fi; " \
118 "else run netboot; fi"
119#define CONFIG_ARP_TIMEOUT 200UL
120
121/* Miscellaneous configurable options */
122#define CONFIG_SYS_LONGHELP /* undef to save memory */
123#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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124#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > "
125#define CONFIG_AUTO_COMPLETE
126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
127
128/* Print Buffer Size */
129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
132
133#define CONFIG_SYS_MEMTEST_START 0x70000000
869aed7b 134#define CONFIG_SYS_MEMTEST_END 0x70010000
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135
136#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
137
138#define CONFIG_SYS_HZ 1000
139#define CONFIG_CMDLINE_EDITING
140
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141/* Physical Memory Map */
142#define CONFIG_NR_DRAM_BANKS 2
143#define PHYS_SDRAM_1 CSD0_BASE_ADDR
144#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
145#define PHYS_SDRAM_2 CSD1_BASE_ADDR
146#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
147#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
148
149#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
150#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
151#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
152
153#define CONFIG_SYS_INIT_SP_OFFSET \
154 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
155#define CONFIG_SYS_INIT_SP_ADDR \
156 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
157
158/* FLASH and environment organization */
159#define CONFIG_SYS_NO_FLASH
160
161#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
162#define CONFIG_ENV_SIZE (8 * 1024)
163#define CONFIG_ENV_IS_IN_MMC
164#define CONFIG_SYS_MMC_ENV_DEV 0
165
166#define CONFIG_OF_LIBFDT
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167
168#endif /* __CONFIG_H */