projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8f393776 SW |
1 | /* |
| 2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | |
| 3 | * | |
| 5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
| 8f393776 SW |
5 | */ |
| 6 | ||
| 7 | #ifndef __MX6_COMMON_H | |
| 8 | #define __MX6_COMMON_H | |
| 9 | ||
| 436cf40f | 10 | #ifndef CONFIG_MX6UL |
| 8f393776 SW |
11 | #define CONFIG_ARM_ERRATA_743622 |
| 12 | #define CONFIG_ARM_ERRATA_751472 | |
| 68659d64 NG |
13 | #define CONFIG_ARM_ERRATA_794072 |
| 14 | #define CONFIG_ARM_ERRATA_761320 | |
| 8f393776 | 15 | |
| 6d73c234 FE |
16 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 17 | #define CONFIG_SYS_L2_PL310 | |
| 18 | #define CONFIG_SYS_PL310_BASE L2_PL310_BASE | |
| 19 | #endif | |
| 20 | ||
| a76df709 | 21 | #define CONFIG_MP |
| 436cf40f PF |
22 | #endif |
| 23 | #define CONFIG_BOARD_POSTCLK_INIT | |
| f13ac7b2 | 24 | #define CONFIG_MXC_GPT_HCLK |
| a76df709 | 25 | |
| 056845c2 PR |
26 | #define CONFIG_SYS_NO_FLASH |
| 27 | ||
| 1ecd2eaa PF |
28 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 |
| 29 | ||
| 056845c2 PR |
30 | #include <linux/sizes.h> |
| 31 | #include <asm/arch/imx-regs.h> | |
| 32 | #include <asm/imx-common/gpio.h> | |
| 056845c2 | 33 | |
| 3b1f6811 PR |
34 | #ifndef CONFIG_MX6 |
| 35 | #define CONFIG_MX6 | |
| 36 | #endif | |
| 37 | ||
| 38 | #define CONFIG_DISPLAY_BOARDINFO | |
| 39 | #define CONFIG_DISPLAY_CPUINFO | |
| 18fb0e3c | 40 | #define CONFIG_SYS_FSL_CLK |
| 3b1f6811 | 41 | |
| ea690917 PR |
42 | /* ATAGs */ |
| 43 | #define CONFIG_CMDLINE_TAG | |
| 44 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 45 | #define CONFIG_INITRD_TAG | |
| 46 | #define CONFIG_REVISION_TAG | |
| 47 | ||
| 81830581 | 48 | /* Boot options */ |
| 94bd1d14 | 49 | #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL)) |
| cd6ddc48 FE |
50 | #define CONFIG_LOADADDR 0x82000000 |
| 51 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 52 | #define CONFIG_SYS_TEXT_BASE 0x87800000 | |
| 53 | #endif | |
| 54 | #else | |
| 81830581 | 55 | #define CONFIG_LOADADDR 0x12000000 |
| 81830581 PR |
56 | #ifndef CONFIG_SYS_TEXT_BASE |
| 57 | #define CONFIG_SYS_TEXT_BASE 0x17800000 | |
| 58 | #endif | |
| cd6ddc48 FE |
59 | #endif |
| 60 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
| 61 | ||
| 81830581 PR |
62 | #ifndef CONFIG_BOOTDELAY |
| 63 | #define CONFIG_BOOTDELAY 3 | |
| 64 | #endif | |
| 65 | ||
| 2d8a0747 PR |
66 | /* allow to overwrite serial and ethaddr */ |
| 67 | #define CONFIG_ENV_OVERWRITE | |
| 68 | #define CONFIG_CONS_INDEX 1 | |
| 69 | #define CONFIG_BAUDRATE 115200 | |
| 70 | ||
| a380ce6e | 71 | /* Filesystems and image support */ |
| a380ce6e | 72 | #define CONFIG_SUPPORT_RAW_INITRD |
| a380ce6e | 73 | #define CONFIG_DOS_PARTITION |
| a380ce6e | 74 | |
| 2d8a0747 | 75 | /* Miscellaneous configurable options */ |
| 2d8a0747 | 76 | #define CONFIG_SYS_LONGHELP |
| 2d8a0747 PR |
77 | #define CONFIG_CMDLINE_EDITING |
| 78 | #define CONFIG_AUTO_COMPLETE | |
| 79 | #define CONFIG_SYS_CBSIZE 512 | |
| 80 | #define CONFIG_SYS_MAXARGS 32 | |
| 81 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 82 | ||
| 1022b85c | 83 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 1022b85c PR |
84 | #endif |
| 85 | ||
| 302b2e5b PR |
86 | /* GPIO */ |
| 87 | #define CONFIG_MXC_GPIO | |
| 302b2e5b | 88 | |
| e51c1e8e PR |
89 | /* MMC */ |
| 90 | #define CONFIG_MMC | |
| e51c1e8e PR |
91 | #define CONFIG_GENERIC_MMC |
| 92 | #define CONFIG_BOUNCE_BUFFER | |
| 93 | #define CONFIG_FSL_ESDHC | |
| 94 | #define CONFIG_FSL_USDHC | |
| 95 | ||
| 3c73b0a4 PR |
96 | /* Fuses */ |
| 97 | #define CONFIG_CMD_FUSE | |
| 98 | #define CONFIG_MXC_OCOTP | |
| 99 | ||
| 8f393776 | 100 | #endif |