projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8f393776 SW |
1 | /* |
| 2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | |
| 3 | * | |
| 5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
| 8f393776 SW |
5 | */ |
| 6 | ||
| 7 | #ifndef __MX6_COMMON_H | |
| 8 | #define __MX6_COMMON_H | |
| 9 | ||
| 436cf40f | 10 | #ifndef CONFIG_MX6UL |
| 8f393776 SW |
11 | #define CONFIG_ARM_ERRATA_743622 |
| 12 | #define CONFIG_ARM_ERRATA_751472 | |
| 68659d64 NG |
13 | #define CONFIG_ARM_ERRATA_794072 |
| 14 | #define CONFIG_ARM_ERRATA_761320 | |
| 8f393776 | 15 | |
| 6d73c234 FE |
16 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 17 | #define CONFIG_SYS_L2_PL310 | |
| 18 | #define CONFIG_SYS_PL310_BASE L2_PL310_BASE | |
| 19 | #endif | |
| 20 | ||
| a76df709 | 21 | #define CONFIG_MP |
| 436cf40f PF |
22 | #endif |
| 23 | #define CONFIG_BOARD_POSTCLK_INIT | |
| f13ac7b2 | 24 | #define CONFIG_MXC_GPT_HCLK |
| a76df709 | 25 | |
| 1ecd2eaa PF |
26 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 |
| 27 | ||
| 056845c2 PR |
28 | #include <linux/sizes.h> |
| 29 | #include <asm/arch/imx-regs.h> | |
| 30 | #include <asm/imx-common/gpio.h> | |
| 056845c2 | 31 | |
| 3b1f6811 PR |
32 | #ifndef CONFIG_MX6 |
| 33 | #define CONFIG_MX6 | |
| 34 | #endif | |
| 35 | ||
| 18fb0e3c | 36 | #define CONFIG_SYS_FSL_CLK |
| 3b1f6811 | 37 | |
| ea690917 PR |
38 | /* ATAGs */ |
| 39 | #define CONFIG_CMDLINE_TAG | |
| 40 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 41 | #define CONFIG_INITRD_TAG | |
| 42 | #define CONFIG_REVISION_TAG | |
| 43 | ||
| 81830581 | 44 | /* Boot options */ |
| 01140119 PF |
45 | #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ |
| 46 | defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL)) | |
| cd6ddc48 FE |
47 | #define CONFIG_LOADADDR 0x82000000 |
| 48 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 49 | #define CONFIG_SYS_TEXT_BASE 0x87800000 | |
| 50 | #endif | |
| 51 | #else | |
| 81830581 | 52 | #define CONFIG_LOADADDR 0x12000000 |
| 81830581 PR |
53 | #ifndef CONFIG_SYS_TEXT_BASE |
| 54 | #define CONFIG_SYS_TEXT_BASE 0x17800000 | |
| 55 | #endif | |
| cd6ddc48 FE |
56 | #endif |
| 57 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
| 58 | ||
| 2d8a0747 PR |
59 | /* allow to overwrite serial and ethaddr */ |
| 60 | #define CONFIG_ENV_OVERWRITE | |
| 61 | #define CONFIG_CONS_INDEX 1 | |
| 62 | #define CONFIG_BAUDRATE 115200 | |
| 63 | ||
| a380ce6e | 64 | /* Filesystems and image support */ |
| a380ce6e | 65 | #define CONFIG_SUPPORT_RAW_INITRD |
| a380ce6e | 66 | |
| 2d8a0747 | 67 | /* Miscellaneous configurable options */ |
| 2d8a0747 | 68 | #define CONFIG_SYS_LONGHELP |
| 2d8a0747 PR |
69 | #define CONFIG_CMDLINE_EDITING |
| 70 | #define CONFIG_AUTO_COMPLETE | |
| 71 | #define CONFIG_SYS_CBSIZE 512 | |
| 72 | #define CONFIG_SYS_MAXARGS 32 | |
| 73 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 74 | ||
| 1022b85c | 75 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 1022b85c PR |
76 | #endif |
| 77 | ||
| 302b2e5b PR |
78 | /* GPIO */ |
| 79 | #define CONFIG_MXC_GPIO | |
| 302b2e5b | 80 | |
| e51c1e8e | 81 | /* MMC */ |
| e51c1e8e PR |
82 | #define CONFIG_BOUNCE_BUFFER |
| 83 | #define CONFIG_FSL_ESDHC | |
| 84 | #define CONFIG_FSL_USDHC | |
| 85 | ||
| 3c73b0a4 PR |
86 | /* Fuses */ |
| 87 | #define CONFIG_CMD_FUSE | |
| 88 | #define CONFIG_MXC_OCOTP | |
| 89 | ||
| e22685d2 GB |
90 | /* Secure boot (HAB) support */ |
| 91 | #ifdef CONFIG_SECURE_BOOT | |
| 92 | #define CONFIG_CSF_SIZE 0x2000 | |
| e22685d2 GB |
93 | #define CONFIG_FSL_CAAM |
| 94 | #define CONFIG_CMD_DEKBLOB | |
| 15b505b0 SE |
95 | #ifdef CONFIG_SPL_BUILD |
| 96 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
| 97 | #endif | |
| e22685d2 GB |
98 | #endif |
| 99 | ||
| 8f393776 | 100 | #endif |