[people/ms/u-boot.git] / include / configs / mx7dsabresd.h

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the Freescale i.MX7D SABRESD board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MX7D_SABRESD_CONFIG_H
#define __MX7D_SABRESD_CONFIG_H

#include "mx7_common.h"

#define CONFIG_DBG_MONITOR
#define PHYS_SDRAM_SIZE			SZ_1G

#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)

/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE             RGMII
#define CONFIG_ETHPRIME                 "FEC"
#define CONFIG_FEC_MXC_PHYADDR          0

#define CONFIG_PHYLIB
#define CONFIG_PHY_BROADCOM
/* ENET1 */
#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR

/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR       0

/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08

#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS

/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED		100000

#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART	1

#ifdef CONFIG_IMX_BOOTAUX
/* Set to QSPI1 A flash at default */
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000

#define UPDATE_M4_ENV \
	"m4image=m4_qspi.bin\0" \
	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
	"update_m4_from_sd=" \
		"if sf probe 0:0; then " \
			"if run loadm4image; then " \
				"setexpr fw_sz ${filesize} + 0xffff; " \
				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
				"sf erase 0x0 ${fw_sz}; " \
				"sf write ${loadaddr} 0x0 ${filesize}; " \
			"fi; " \
		"fi\0" \
	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
#else
#define UPDATE_M4_ENV ""
#endif

#define CONFIG_MFG_ENV_SETTINGS \
	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
		"rdinit=/linuxrc " \
		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
		"g_mass_storage.iSerialNumber=\"\" "\
		"clk_ignore_unused "\
		"\0" \
	"initrd_addr=0x83800000\0" \
	"initrd_high=0xffffffff\0" \
	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \

#define CONFIG_DFU_ENV_SETTINGS \
	"dfu_alt_info=image raw 0 0x800000;"\
		"u-boot raw 0 0x4000;"\
		"bootimg part 0 1;"\
		"rootfs part 0 2\0" \

#define CONFIG_EXTRA_ENV_SETTINGS \
	UPDATE_M4_ENV \
	CONFIG_MFG_ENV_SETTINGS \
	CONFIG_DFU_ENV_SETTINGS \
	"script=boot.scr\0" \
	"image=zImage\0" \
	"console=ttymxc0\0" \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"fdt_file=imx7d-sdb.dtb\0" \
	"fdt_addr=0x83000000\0" \
	"boot_fdt=try\0" \
	"ip_dyn=yes\0" \
	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	"mmcautodetect=yes\0" \
	"mmcargs=setenv bootargs console=${console},${baudrate} " \
		"root=${mmcroot}\0" \
	"loadbootscript=" \
		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
			"if run loadfdt; then " \
				"bootz ${loadaddr} - ${fdt_addr}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo WARN: Cannot load the DT; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0" \
	"netargs=setenv bootargs console=${console},${baudrate} " \
		"root=/dev/nfs " \
	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
		"netboot=echo Booting from net ...; " \
		"run netargs; " \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"${get_cmd} ${image}; " \
		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
				"bootz ${loadaddr} - ${fdt_addr}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo WARN: Cannot load the DT; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0"

#define CONFIG_BOOTCOMMAND \
	   "mmc dev ${mmcdev};" \
	   "mmc dev ${mmcdev}; if mmc rescan; then " \
		   "if run loadbootscript; then " \
			   "run bootscript; " \
		   "else " \
			   "if run loadimage; then " \
				   "run mmcboot; " \
			   "else run netboot; " \
			   "fi; " \
		   "fi; " \
	   "else run netboot; fi"

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
#define CONFIG_SYS_HZ			1000

#define CONFIG_STACKSIZE		SZ_128K

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#define CONFIG_ENV_SIZE			SZ_8K
#define CONFIG_ENV_IS_IN_MMC

/* MXC SPI driver support */
#define CONFIG_MXC_SPI

/*
 * If want to use nand, define CONFIG_NAND_MXS and rework board
 * to support nand, since emmc has pin conflicts with nand
 */
#ifdef CONFIG_NAND_MXS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS

/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION

/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
#endif

#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
#ifdef CONFIG_NAND_MXS
#define CONFIG_SYS_FSL_USDHC_NUM	1
#else
#define CONFIG_SYS_FSL_USDHC_NUM	2
#endif

#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */

/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS   0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

#define CONFIG_IMX_THERMAL

#define CONFIG_USBD_HS

#define CONFIG_USB_FUNCTION_MASS_STORAGE

#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#endif

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		40000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#define FSL_QSPI_FLASH_NUM		1
#define FSL_QSPI_FLASH_SIZE		SZ_64M
#define QSPI0_BASE_ADDR			QSPI1_IPS_BASE_ADDR
#define QSPI0_AMBA_BASE			QSPI0_ARB_BASE_ADDR
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
1a8150d4 AA	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* Configuration settings for the Freescale i.MX7D SABRESD board.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __MX7D_SABRESD_CONFIG_H
	10	#define __MX7D_SABRESD_CONFIG_H
	11
	12	#include "mx7_common.h"
	13
	14	#define CONFIG_DBG_MONITOR
	15	#define PHYS_SDRAM_SIZE SZ_1G
	16
5d69269d FE	17	#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
5d69269d FE	18
6baa2616 FE	19	/* Size of malloc() pool */
	20	#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
	21
1a8150d4	22	/* Network */
1a8150d4 AA	23	#define CONFIG_FEC_MXC
	24	#define CONFIG_MII
	25	#define CONFIG_FEC_XCV_TYPE RGMII
	26	#define CONFIG_ETHPRIME "FEC"
	27	#define CONFIG_FEC_MXC_PHYADDR 0
	28
	29	#define CONFIG_PHYLIB
	30	#define CONFIG_PHY_BROADCOM
1a8150d4 AA	31	/* ENET1 */
	32	#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
	33
	34	/* MMC Config*/
	35	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	36
	37	/* PMIC */
	38	#define CONFIG_POWER
	39	#define CONFIG_POWER_I2C
	40	#define CONFIG_POWER_PFUZE3000
	41	#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
	42
	43	#undef CONFIG_BOOTM_NETBSD
	44	#undef CONFIG_BOOTM_PLAN9
	45	#undef CONFIG_BOOTM_RTEMS
	46
1a8150d4	47	/* I2C configs */
1a8150d4 AA	48	#define CONFIG_SYS_I2C
1a8150d4 AA	49	#define CONFIG_SYS_I2C_MXC
03544c66	50	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
1a8150d4 AA	51	#define CONFIG_SYS_I2C_SPEED 100000
	52
	53	#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
	54	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
	55
79e355fb PF	56	#ifdef CONFIG_IMX_BOOTAUX
	57	/* Set to QSPI1 A flash at default */
	58	#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
79e355fb PF	59
	60	#define UPDATE_M4_ENV \
	61	"m4image=m4_qspi.bin\0" \
	62	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
	63	"update_m4_from_sd=" \
	64	"if sf probe 0:0; then " \
	65	"if run loadm4image; then " \
	66	"setexpr fw_sz ${filesize} + 0xffff; " \
	67	"setexpr fw_sz ${fw_sz} / 0x10000; " \
	68	"setexpr fw_sz ${fw_sz} * 0x10000; " \
	69	"sf erase 0x0 ${fw_sz}; " \
	70	"sf write ${loadaddr} 0x0 ${filesize}; " \
	71	"fi; " \
	72	"fi\0" \
	73	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
	74	#else
	75	#define UPDATE_M4_ENV ""
	76	#endif
	77
1a8150d4 AA	78	#define CONFIG_MFG_ENV_SETTINGS \
	79	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
	80	"rdinit=/linuxrc " \
	81	"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
	82	"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
	83	"g_mass_storage.iSerialNumber=\"\" "\
	84	"clk_ignore_unused "\
	85	"\0" \
	86	"initrd_addr=0x83800000\0" \
	87	"initrd_high=0xffffffff\0" \
	88	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
	89
73f1b80c TJL	90	#define CONFIG_DFU_ENV_SETTINGS \
	91	"dfu_alt_info=image raw 0 0x800000;"\
	92	"u-boot raw 0 0x4000;"\
	93	"bootimg part 0 1;"\
	94	"rootfs part 0 2\0" \
	95
1a8150d4	96	#define CONFIG_EXTRA_ENV_SETTINGS \
79e355fb	97	UPDATE_M4_ENV \
1a8150d4	98	CONFIG_MFG_ENV_SETTINGS \
73f1b80c	99	CONFIG_DFU_ENV_SETTINGS \
1a8150d4 AA	100	"script=boot.scr\0" \
	101	"image=zImage\0" \
	102	"console=ttymxc0\0" \
	103	"fdt_high=0xffffffff\0" \
	104	"initrd_high=0xffffffff\0" \
	105	"fdt_file=imx7d-sdb.dtb\0" \
	106	"fdt_addr=0x83000000\0" \
	107	"boot_fdt=try\0" \
	108	"ip_dyn=yes\0" \
ebe517b6	109	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
1a8150d4 AA	110	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	111	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	112	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	113	"mmcautodetect=yes\0" \
	114	"mmcargs=setenv bootargs console=${console},${baudrate} " \
	115	"root=${mmcroot}\0" \
	116	"loadbootscript=" \
	117	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	118	"bootscript=echo Running bootscript from mmc ...; " \
	119	"source\0" \
	120	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	121	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	122	"mmcboot=echo Booting from mmc ...; " \
	123	"run mmcargs; " \
	124	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	125	"if run loadfdt; then " \
	126	"bootz ${loadaddr} - ${fdt_addr}; " \
	127	"else " \
	128	"if test ${boot_fdt} = try; then " \
	129	"bootz; " \
	130	"else " \
	131	"echo WARN: Cannot load the DT; " \
	132	"fi; " \
	133	"fi; " \
	134	"else " \
	135	"bootz; " \
	136	"fi;\0" \
	137	"netargs=setenv bootargs console=${console},${baudrate} " \
	138	"root=/dev/nfs " \
	139	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	140	"netboot=echo Booting from net ...; " \
	141	"run netargs; " \
	142	"if test ${ip_dyn} = yes; then " \
	143	"setenv get_cmd dhcp; " \
	144	"else " \
	145	"setenv get_cmd tftp; " \
	146	"fi; " \
	147	"${get_cmd} ${image}; " \
	148	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	149	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
	150	"bootz ${loadaddr} - ${fdt_addr}; " \
	151	"else " \
	152	"if test ${boot_fdt} = try; then " \
	153	"bootz; " \
	154	"else " \
	155	"echo WARN: Cannot load the DT; " \
	156	"fi; " \
	157	"fi; " \
	158	"else " \
	159	"bootz; " \
	160	"fi;\0"
	161
	162	#define CONFIG_BOOTCOMMAND \
	163	"mmc dev ${mmcdev};" \
	164	"mmc dev ${mmcdev}; if mmc rescan; then " \
	165	"if run loadbootscript; then " \
	166	"run bootscript; " \
	167	"else " \
	168	"if run loadimage; then " \
	169	"run mmcboot; " \
	170	"else run netboot; " \
	171	"fi; " \
	172	"fi; " \
	173	"else run netboot; fi"
174
1a8150d4 AA	175	#define CONFIG_SYS_MEMTEST_START 0x80000000
	176	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
	177
	178	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	179	#define CONFIG_SYS_HZ 1000
	180
	181	#define CONFIG_STACKSIZE SZ_128K
	182
	183	/* Physical Memory Map */
	184	#define CONFIG_NR_DRAM_BANKS 1
	185	#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	186
	187	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	188	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	189	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	190
	191	#define CONFIG_SYS_INIT_SP_OFFSET \
	192	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	193	#define CONFIG_SYS_INIT_SP_ADDR \
	194	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	195
e856bdcf	196	/* environment organization */
1a8150d4 AA	197	#define CONFIG_ENV_SIZE SZ_8K
1a8150d4 AA	198	#define CONFIG_ENV_IS_IN_MMC
6e1a41cd	199
9cd37b02 AA	200	/* MXC SPI driver support */
	201	#define CONFIG_MXC_SPI
	202
6e1a41cd PF	203	/*
	204	* If want to use nand, define CONFIG_NAND_MXS and rework board
	205	* to support nand, since emmc has pin conflicts with nand
	206	*/
	207	#ifdef CONFIG_NAND_MXS
	208	#define CONFIG_CMD_NAND
	209	#define CONFIG_CMD_NAND_TRIMFFS
	210
	211	/* NAND stuff */
	212	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	213	#define CONFIG_SYS_NAND_BASE 0x40000000
	214	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	215	#define CONFIG_SYS_NAND_ONFI_DETECTION
	216
	217	/* DMA stuff, needed for GPMI/MXS NAND support */
	218	#define CONFIG_APBH_DMA
	219	#define CONFIG_APBH_DMA_BURST
	220	#define CONFIG_APBH_DMA_BURST8
	221	#endif
	222
1a8150d4	223	#define CONFIG_ENV_OFFSET (8 * SZ_64K)
6e1a41cd PF	224	#ifdef CONFIG_NAND_MXS
	225	#define CONFIG_SYS_FSL_USDHC_NUM 1
	226	#else
1a8150d4	227	#define CONFIG_SYS_FSL_USDHC_NUM 2
6e1a41cd	228	#endif
1a8150d4 AA	229
	230	#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
	231	#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
	232	#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
	233
1a8150d4	234	/* USB Configs */
1a8150d4 AA	235	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	236	#define CONFIG_USB_HOST_ETHER
	237	#define CONFIG_USB_ETHER_ASIX
	238	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	239	#define CONFIG_MXC_USB_FLAGS 0
	240	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	241
	242	#define CONFIG_IMX_THERMAL
	243
73f1b80c	244	#define CONFIG_USBD_HS
73f1b80c	245
73f1b80c	246	#define CONFIG_USB_FUNCTION_MASS_STORAGE
73f1b80c	247
ebe517b6	248	#ifdef CONFIG_VIDEO
ebe517b6 PF	249	#define CONFIG_VIDEO_MXS
ebe517b6 PF	250	#define CONFIG_VIDEO_LOGO
ebe517b6 PF	251	#define CONFIG_SPLASH_SCREEN
	252	#define CONFIG_SPLASH_SCREEN_ALIGN
	253	#define CONFIG_CMD_BMP
	254	#define CONFIG_BMP_16BPP
	255	#define CONFIG_VIDEO_BMP_RLE8
	256	#define CONFIG_VIDEO_BMP_LOGO
	257	#endif
	258
53cc647d	259	#ifdef CONFIG_FSL_QSPI
53cc647d PF	260	#define CONFIG_SPI_FLASH
	261	#define CONFIG_SPI_FLASH_MACRONIX
	262	#define CONFIG_SPI_FLASH_BAR
	263	#define CONFIG_SF_DEFAULT_BUS 0
	264	#define CONFIG_SF_DEFAULT_CS 0
	265	#define CONFIG_SF_DEFAULT_SPEED 40000000
	266	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	267	#define FSL_QSPI_FLASH_NUM 1
	268	#define FSL_QSPI_FLASH_SIZE SZ_64M
	269	#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
	270	#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
	271	#endif
	272
1a8150d4	273	#endif /* __CONFIG_H */