[people/ms/u-boot.git] / include / configs / mxs.h

/*
 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIGS_MXS_H__
#define __CONFIGS_MXS_H__

/*
 * Includes
 */

#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
#error Select one of CONFIG_MX23 or CONFIG_MX28 !
#endif

#include <asm/arch/regs-base.h>

#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
#elif defined(CONFIG_MX28)
#include <asm/arch/iomux-mx28.h>
#endif

/*
 * CPU specifics
 */

/* Startup hooks */

/* SPL */
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"

/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */

/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
#if defined(CONFIG_MX23)
#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
#elif defined(CONFIG_MX28)
#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
#endif

/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
 * binary. In case there was more of this mess, 0x100 bytes are skipped.
 *
 * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
 * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
 * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
 *
 * As for the SPL, we must avoid the first 4 KiB as well, but we load the
 * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
 */
#define CONFIG_SPL_TEXT_BASE		0x00001000

/* U-Boot general configuration */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */

/* Booting Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

/*
 * Drivers
 */

/* APBH DMA */

/* GPIO */
#define CONFIG_MXS_GPIO

/*
 * DUART Serial Driver.
 * Conflicts with AUART driver which can be set by board.
 */
#define CONFIG_PL011_CLOCK		24000000
#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX		0
/* Default baudrate can be overridden by board! */

/* FEC Ethernet on SoC */
#ifdef CONFIG_FEC_MXC
#define CONFIG_MII
#ifndef CONFIG_ETHPRIME
#define CONFIG_ETHPRIME			"FEC0"
#endif
#ifndef CONFIG_FEC_XCV_TYPE
#define CONFIG_FEC_XCV_TYPE		RMII
#endif
#endif

/* LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
#endif

/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
#endif

/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif

/* OCOTP */
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXS_OCOTP
#endif

/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_SPI_HALF_DUPLEX
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_IS_TDI
#endif

#endif	/* __CONFIGS_MXS_H__ */
Commit	Line	Data
5434caf5 MV	1	/*
	2	* Copyright (C) 2013 Marek Vasut <marex@denx.de>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*/
	19	#ifndef __CONFIGS_MXS_H__
	20	#define __CONFIGS_MXS_H__
	21
	22	/*
	23	* Includes
	24	*/
	25
	26	#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
	27	#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
	28	#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
	29	#error Select one of CONFIG_MX23 or CONFIG_MX28 !
	30	#endif
	31
	32	#include <asm/arch/regs-base.h>
	33
	34	#if defined(CONFIG_MX23)
	35	#include <asm/arch/iomux-mx23.h>
	36	#elif defined(CONFIG_MX28)
	37	#include <asm/arch/iomux-mx28.h>
	38	#endif
	39
	40	/*
	41	* CPU specifics
	42	*/
	43
5434caf5	44	/* Startup hooks */
5434caf5 MV	45
5434caf5 MV	46	/* SPL */
5434caf5 MV	47	#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
5434caf5 MV	48	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
5434caf5 MV	49
	50	/* Memory sizes */
	51	#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
5434caf5 MV	52	#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
	53	#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
	54
	55	/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
	56	#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
	57	#if defined(CONFIG_MX23)
	58	#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
	59	#elif defined(CONFIG_MX28)
	60	#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
	61	#endif
	62
	63	/* Point initial SP in SRAM so SPL can use it too. */
	64	#define CONFIG_SYS_INIT_SP_OFFSET \
	65	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	66	#define CONFIG_SYS_INIT_SP_ADDR \
	67	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	68
	69	/*
	70	* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
	71	* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
	72	* binary. In case there was more of this mess, 0x100 bytes are skipped.
9c2c8a31 MV	73	*
	74	* In case of a HAB boot, we cannot for some weird reason use the first 4KiB
	75	* of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
	76	* blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
	77	*
	78	* As for the SPL, we must avoid the first 4 KiB as well, but we load the
	79	* IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
5434caf5	80	*/
9c2c8a31	81	#define CONFIG_SPL_TEXT_BASE 0x00001000
5434caf5 MV	82
5434caf5 MV	83	/* U-Boot general configuration */
5434caf5	84	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5434caf5 MV	85	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	86	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	87	/* Boot argument buffer size */
5434caf5 MV	88
	89	/* Booting Linux */
	90	#define CONFIG_CMDLINE_TAG
	91	#define CONFIG_SETUP_MEMORY_TAGS
	92
	93	/*
	94	* Drivers
	95	*/
	96
	97	/* APBH DMA */
5434caf5 MV	98
	99	/* GPIO */
	100	#define CONFIG_MXS_GPIO
	101
0cfb8afe AW	102	/*
	103	* DUART Serial Driver.
	104	* Conflicts with AUART driver which can be set by board.
	105	*/
5434caf5 MV	106	#define CONFIG_PL011_CLOCK 24000000
	107	#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
	108	#define CONFIG_CONS_INDEX 0
62a3b7dd	109	/* Default baudrate can be overridden by board! */
5434caf5 MV	110
	111	/* FEC Ethernet on SoC */
	112	#ifdef CONFIG_FEC_MXC
	113	#define CONFIG_MII
	114	#ifndef CONFIG_ETHPRIME
	115	#define CONFIG_ETHPRIME "FEC0"
	116	#endif
	117	#ifndef CONFIG_FEC_XCV_TYPE
	118	#define CONFIG_FEC_XCV_TYPE RMII
	119	#endif
	120	#endif
	121
5434caf5 MV	122	/* LCD */
5434caf5 MV	123	#ifdef CONFIG_VIDEO
5434caf5	124	#define CONFIG_VIDEO_MXS
5434caf5 MV	125	#endif
	126
	127	/* MMC */
	128	#ifdef CONFIG_CMD_MMC
5434caf5	129	#define CONFIG_BOUNCE_BUFFER
5434caf5 MV	130	#endif
	131
	132	/* NAND */
	133	#ifdef CONFIG_CMD_NAND
5434caf5 MV	134	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	135	#define CONFIG_SYS_NAND_BASE 0x60000000
	136	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	137	#endif
	138
2bbcccf5 MV	139	/* OCOTP */
	140	#ifdef CONFIG_CMD_FUSE
	141	#define CONFIG_MXS_OCOTP
	142	#endif
	143
5434caf5 MV	144	/* SPI */
	145	#ifdef CONFIG_CMD_SPI
	146	#define CONFIG_HARD_SPI
5434caf5 MV	147	#define CONFIG_SPI_HALF_DUPLEX
	148	#endif
	149
	150	/* USB */
	151	#ifdef CONFIG_CMD_USB
5434caf5 MV	152	#define CONFIG_USB_EHCI_MXS
	153	#define CONFIG_EHCI_IS_TDI
	154	#endif
	155
	156	#endif /* __CONFIGS_MXS_H__ */