[people/ms/u-boot.git] / include / configs / mxs.h

/*
 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIGS_MXS_H__
#define __CONFIGS_MXS_H__

/*
 * Includes
 */

#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
#error Select one of CONFIG_MX23 or CONFIG_MX28 !
#endif

#include <asm/arch/regs-base.h>

#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
#elif defined(CONFIG_MX28)
#include <asm/arch/iomux-mx28.h>
#endif

/*
 * CPU specifics
 */

/* Startup hooks */

/* SPL */
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"

/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */

/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
#if defined(CONFIG_MX23)
#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
#elif defined(CONFIG_MX28)
#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
#endif

/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
 * binary. In case there was more of this mess, 0x100 bytes are skipped.
 *
 * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
 * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
 * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
 *
 * As for the SPL, we must avoid the first 4 KiB as well, but we load the
 * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
 */
#define CONFIG_SYS_TEXT_BASE		0x40002000
#define CONFIG_SPL_TEXT_BASE		0x00001000

/* U-Boot general configuration */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

/* Booting Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

/*
 * Drivers
 */

/* APBH DMA */
#define CONFIG_APBH_DMA

/* GPIO */
#define CONFIG_MXS_GPIO

/*
 * DUART Serial Driver.
 * Conflicts with AUART driver which can be set by board.
 */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK		24000000
#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX		0
/* Default baudrate can be overridden by board! */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE			115200
#endif

/* FEC Ethernet on SoC */
#ifdef CONFIG_FEC_MXC
#define CONFIG_MII
#ifndef CONFIG_ETHPRIME
#define CONFIG_ETHPRIME			"FEC0"
#endif
#ifndef CONFIG_FEC_XCV_TYPE
#define CONFIG_FEC_XCV_TYPE		RMII
#endif
#endif

/* I2C */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXS
#define CONFIG_HARD_I2C
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED		400000
#endif
#endif

/* LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
#endif

/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#endif

/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif

/* OCOTP */
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXS_OCOTP
#endif

/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#define CONFIG_SPI_HALF_DUPLEX
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_IS_TDI
#endif

#endif	/* __CONFIGS_MXS_H__ */
Commit	Line	Data
5434caf5 MV	1	/*
	2	* Copyright (C) 2013 Marek Vasut <marex@denx.de>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*/
	19	#ifndef __CONFIGS_MXS_H__
	20	#define __CONFIGS_MXS_H__
	21
	22	/*
	23	* Includes
	24	*/
	25
	26	#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
	27	#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
	28	#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
	29	#error Select one of CONFIG_MX23 or CONFIG_MX28 !
	30	#endif
	31
	32	#include <asm/arch/regs-base.h>
	33
	34	#if defined(CONFIG_MX23)
	35	#include <asm/arch/iomux-mx23.h>
	36	#elif defined(CONFIG_MX28)
	37	#include <asm/arch/iomux-mx28.h>
	38	#endif
	39
	40	/*
	41	* CPU specifics
	42	*/
	43
5434caf5	44	/* Startup hooks */
5434caf5 MV	45
5434caf5 MV	46	/* SPL */
5434caf5 MV	47	#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
	48	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
	49	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
5434caf5 MV	50
	51	/* Memory sizes */
	52	#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
5434caf5 MV	53	#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
	54	#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
	55
	56	/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
	57	#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
	58	#if defined(CONFIG_MX23)
	59	#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
	60	#elif defined(CONFIG_MX28)
	61	#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
	62	#endif
	63
	64	/* Point initial SP in SRAM so SPL can use it too. */
	65	#define CONFIG_SYS_INIT_SP_OFFSET \
	66	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	67	#define CONFIG_SYS_INIT_SP_ADDR \
	68	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	69
	70	/*
	71	* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
	72	* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
	73	* binary. In case there was more of this mess, 0x100 bytes are skipped.
9c2c8a31 MV	74	*
	75	* In case of a HAB boot, we cannot for some weird reason use the first 4KiB
	76	* of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
	77	* blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
	78	*
	79	* As for the SPL, we must avoid the first 4 KiB as well, but we load the
	80	* IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
5434caf5	81	*/
9c2c8a31 MV	82	#define CONFIG_SYS_TEXT_BASE 0x40002000
9c2c8a31 MV	83	#define CONFIG_SPL_TEXT_BASE 0x00001000
5434caf5 MV	84
	85	/* U-Boot general configuration */
	86	#define CONFIG_SYS_LONGHELP
5434caf5	87	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5434caf5 MV	88	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	89	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	90	/* Boot argument buffer size */
5434caf5 MV	91	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
5434caf5 MV	92	#define CONFIG_CMDLINE_EDITING /* Command history etc */
5434caf5 MV	93
	94	/* Booting Linux */
	95	#define CONFIG_CMDLINE_TAG
	96	#define CONFIG_SETUP_MEMORY_TAGS
	97
	98	/*
	99	* Drivers
	100	*/
	101
	102	/* APBH DMA */
	103	#define CONFIG_APBH_DMA
	104
	105	/* GPIO */
	106	#define CONFIG_MXS_GPIO
	107
0cfb8afe AW	108	/*
	109	* DUART Serial Driver.
	110	* Conflicts with AUART driver which can be set by board.
	111	*/
5434caf5 MV	112	#define CONFIG_PL011_SERIAL
	113	#define CONFIG_PL011_CLOCK 24000000
	114	#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
	115	#define CONFIG_CONS_INDEX 0
62a3b7dd	116	/* Default baudrate can be overridden by board! */
5434caf5 MV	117	#ifndef CONFIG_BAUDRATE
	118	#define CONFIG_BAUDRATE 115200
	119	#endif
	120
	121	/* FEC Ethernet on SoC */
	122	#ifdef CONFIG_FEC_MXC
	123	#define CONFIG_MII
	124	#ifndef CONFIG_ETHPRIME
	125	#define CONFIG_ETHPRIME "FEC0"
	126	#endif
	127	#ifndef CONFIG_FEC_XCV_TYPE
	128	#define CONFIG_FEC_XCV_TYPE RMII
	129	#endif
	130	#endif
	131
	132	/* I2C */
	133	#ifdef CONFIG_CMD_I2C
1fa96e80 MV	134	#define CONFIG_SYS_I2C
1fa96e80 MV	135	#define CONFIG_SYS_I2C_MXS
5434caf5 MV	136	#define CONFIG_HARD_I2C
	137	#ifndef CONFIG_SYS_I2C_SPEED
	138	#define CONFIG_SYS_I2C_SPEED 400000
	139	#endif
	140	#endif
	141
	142	/* LCD */
	143	#ifdef CONFIG_VIDEO
5434caf5	144	#define CONFIG_VIDEO_MXS
5434caf5 MV	145	#endif
	146
	147	/* MMC */
	148	#ifdef CONFIG_CMD_MMC
5434caf5 MV	149	#define CONFIG_GENERIC_MMC
5434caf5 MV	150	#define CONFIG_BOUNCE_BUFFER
5434caf5 MV	151	#endif
	152
	153	/* NAND */
	154	#ifdef CONFIG_CMD_NAND
	155	#define CONFIG_NAND_MXS
	156	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	157	#define CONFIG_SYS_NAND_BASE 0x60000000
	158	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	159	#endif
	160
2bbcccf5 MV	161	/* OCOTP */
	162	#ifdef CONFIG_CMD_FUSE
	163	#define CONFIG_MXS_OCOTP
	164	#endif
	165
5434caf5 MV	166	/* SPI */
	167	#ifdef CONFIG_CMD_SPI
	168	#define CONFIG_HARD_SPI
	169	#define CONFIG_MXS_SPI
	170	#define CONFIG_SPI_HALF_DUPLEX
	171	#endif
	172
	173	/* USB */
	174	#ifdef CONFIG_CMD_USB
	175	#define CONFIG_USB_EHCI
	176	#define CONFIG_USB_EHCI_MXS
	177	#define CONFIG_EHCI_IS_TDI
	178	#endif
	179
	180	#endif /* __CONFIGS_MXS_H__ */