[people/ms/u-boot.git] / include / configs / netstar.h

/*
 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
 *
 * Configuation settings for the TI OMAP NetStar board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <configs/omap1510.h>

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM925T	1		/* This is an arm925t CPU */
#define CONFIG_OMAP	1		/* in a TI OMAP core */
#define CONFIG_OMAP1510 1		/* which is in a 5910 */

/* Input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
#define CONFIG_XTAL_FREQ	12000000

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

#define CONFIG_MISC_INIT_R		/* There is nothing to really init */
#define BOARD_LATE_INIT			/* but we flash the LEDs here */

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
#define CONFIG_SYS_CONSOLE_INFO_QUIET

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define PHYS_FLASH_1_SIZE	(1 * 1024 * 1024)
#define CONFIG_SYS_MAX_FLASH_SECT	19
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* in ticks */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ)

#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		0x4000
#define CONFIG_ENV_SIZE		(8 * 1024)
#define CONFIG_ENV_SECT_SIZE	(8 * 1024)
#define CONFIG_ENV_ADDR_REDUND	0x6000
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

/*
 * The stack size is set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(1 * 1024 * 1024)	/* regular stack */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE	0x04000300

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
/*#define CONFIG_SKIP_LOWLEVEL_INIT */

/*
 * NAND flash
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE	0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL	1

/*
 * partitions (mtdparts command line support)
 */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
#define MTDPARTS_DEFAULT	"mtdparts=" \
	"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
	"omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN


#define CONFIG_JFFS2_NAND	1	/* jffs2 on nand support */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_LOOPW

#define CONFIG_BOOTDELAY	3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
#define CONFIG_BOOTCOMMAND	"run fboot"
#define CONFIG_PREBOOT		"run setup"
#define	CONFIG_EXTRA_ENV_SETTINGS						\
	"autostart=yes\0"							\
	"ospart=0\0"								\
	"setup=setenv bootargs console=ttyS0,$baudrate "			\
		"$mtdparts\0"							\
	"setpart="								\
	"if test -n $swapos; then "						\
		"setenv swapos; saveenv; "					\
	"else "									\
		"if test $ospart -eq 0; then setenv ospart 1;"			\
			"else setenv ospart 0;		fi; "			\
	"fi\0"									\
	"nfsargs=setenv bootargs $bootargs "					\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off "	\
		"nfsroot=$rootpath root=/dev/nfs\0"				\
	"flashargs=run setpart;setenv bootargs $bootargs "			\
		"root=mtd:rootfs$ospart ro "					\
		"rootfstype=jffs2\0"						\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"		\
	"fboot=run flashargs;nboot kernel$ospart\0"				\
	"nboot=bootp;run nfsargs;tftp\0"

#if 0	/* feel free to disable for development */
#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
#define CONFIG_AUTOBOOT_PROMPT		\
	"\nNetStar PBX - boot in %d secs...\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"."	/* 1st "password"	*/
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
				(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)

#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */

/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
 * This time is further subdivided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
#define CONFIG_SYS_PVT			7		/* 2^(pvt+1), divide by 256 */
#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))

#define OMAP5910_DPLL_DIV	1
#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)

#define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
#define OMAP5910_LCD_DIV	2	/* CKL/4 */
#define OMAP5910_ARM_DIV	0	/* CKL/1 */
#define OMAP5910_DSP_DIV	0	/* CKL/1 */
#define OMAP5910_TC_DIV		1	/* CKL/2 */
#define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
#define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */

#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
#define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
				 (OMAP5910_LCD_DIV << 2) |	\
				 (OMAP5910_ARM_DIV << 4) |	\
				 (OMAP5910_DSP_DIV << 6) |	\
				 (OMAP5910_TC_DIV << 8) |	\
				 (OMAP5910_DSP_MMU_DIV << 10) |	\
				 (OMAP5910_ARM_TIM_SEL << 12))

#endif	/* __CONFIG_H */
Commit	Line	Data
ac7eb8a3 WD	1	/*
	2	* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
	3	*
	4	* Configuation settings for the TI OMAP NetStar board.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include <configs/omap1510.h>
	29
	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34	#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP1510 1 /* which is in a 5910 */
	37
	38	/* Input clock of PLL */
	39	#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
	40	#define CONFIG_XTAL_FREQ 12000000
	41
	42	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	43
	44	#define CONFIG_MISC_INIT_R /* There is nothing to really init */
	45	#define BOARD_LATE_INIT /* but we flash the LEDs here */
	46
	47	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	48	#define CONFIG_SETUP_MEMORY_TAGS 1
	49	#define CONFIG_INITRD_TAG 1
	50
ac7eb8a3	51	#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
6d0f6bcf	52	#define CONFIG_SYS_CONSOLE_INFO_QUIET
ac7eb8a3 WD	53
	54	/*
	55	* Physical Memory Map
	56	*/
	57	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	58	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
f4e7cbfc	59	#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
ac7eb8a3 WD	60	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	61
	62	/*
	63	* FLASH organization
	64	*/
6d0f6bcf JCPV	65	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
6d0f6bcf JCPV	66	#define CONFIG_SYS_MAX_FLASH_BANKS 1
f4e7cbfc	67	#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024)
6d0f6bcf JCPV	68	#define CONFIG_SYS_MAX_FLASH_SECT 19
	69	#define CONFIG_SYS_FLASH_ERASE_TOUT (5CONFIG_SYS_HZ) / in ticks */
	70	#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ)
ac7eb8a3	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
6d0f6bcf JCPV	73	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
ac7eb8a3 WD	74
	75	/*
	76	* Environment settings
	77	*/
5a1aceb0	78	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	79	#define CONFIG_ENV_ADDR 0x4000
	80	#define CONFIG_ENV_SIZE (8 * 1024)
	81	#define CONFIG_ENV_SECT_SIZE (8 * 1024)
	82	#define CONFIG_ENV_ADDR_REDUND 0x6000
	83	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
ac7eb8a3 WD	84	#define CONFIG_ENV_OVERWRITE
	85
	86	/*
	87	* Size of malloc() pool
	88	*/
6d0f6bcf JCPV	89	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
6d0f6bcf JCPV	90	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
ac7eb8a3 WD	91
	92	/*
	93	* The stack size is set up in start.S using the settings below
	94	*/
f4e7cbfc	95	#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */
ac7eb8a3 WD	96
	97	/*
	98	* Hardware drivers
	99	*/
	100	#define CONFIG_DRIVER_SMC91111
	101	#define CONFIG_SMC91111_BASE 0x04000300
	102
	103	/*
	104	* NS16550 Configuration
	105	*/
6d0f6bcf JCPV	106	#define CONFIG_SYS_NS16550
	107	#define CONFIG_SYS_NS16550_SERIAL
	108	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	109	#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
	110	#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
ac7eb8a3 WD	111
	112	#define CONFIG_CONS_INDEX 1
	113	#define CONFIG_BAUDRATE 115200
6d0f6bcf	114	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
ac7eb8a3 WD	115
	116	/#define CONFIG_SKIP_RELOCATE_UBOOT/
	117	/#define CONFIG_SKIP_LOWLEVEL_INIT /
	118
	119	/*
	120	* NAND flash
	121	*/
6d0f6bcf	122	#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf	123	#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
f4e7cbfc	124	#define NAND_ALLOW_ERASE_ALL 1
ac7eb8a3 WD	125
ac7eb8a3 WD	126	/*
f4e7cbfc	127	* partitions (mtdparts command line support)
ac7eb8a3 WD	128	*/
	129	#define CONFIG_JFFS2_CMDLINE
	130	#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
f4e7cbfc PP	131	#define MTDPARTS_DEFAULT "mtdparts=" \
	132	"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
	133	"omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
ac7eb8a3	134
ac7eb8a3	135
929a2bfd JL	136	/*
	137	* Command line configuration.
	138	*/
	139
	140	#define CONFIG_CMD_BDI
	141	#define CONFIG_CMD_BOOTD
	142	#define CONFIG_CMD_DHCP
bdab39d3	143	#define CONFIG_CMD_SAVEENV
929a2bfd JL	144	#define CONFIG_CMD_FLASH
	145	#define CONFIG_CMD_IMI
	146	#define CONFIG_CMD_JFFS2
	147	#define CONFIG_CMD_LOADB
	148	#define CONFIG_CMD_MEMORY
	149	#define CONFIG_CMD_NAND
	150	#define CONFIG_CMD_NET
	151	#define CONFIG_CMD_PING
	152	#define CONFIG_CMD_RUN
	153
ac7eb8a3 WD	154
ac7eb8a3 WD	155	#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
ac7eb8a3	156
d3b8c1a7 JL	157	/*
	158	* BOOTP options
	159	*/
	160	#define CONFIG_BOOTP_SUBNETMASK
	161	#define CONFIG_BOOTP_GATEWAY
	162	#define CONFIG_BOOTP_HOSTNAME
	163	#define CONFIG_BOOTP_BOOTPATH
	164
ac7eb8a3 WD	165	#define CONFIG_LOOPW
ac7eb8a3 WD	166
ac7eb8a3 WD	167	#define CONFIG_BOOTDELAY 3
	168	#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
	169	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
6d0f6bcf	170	#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
f4e7cbfc	171	#define CONFIG_BOOTCOMMAND "run fboot"
ac7eb8a3	172	#define CONFIG_PREBOOT "run setup"
f4e7cbfc PP	173	#define CONFIG_EXTRA_ENV_SETTINGS \
	174	"autostart=yes\0" \
	175	"ospart=0\0" \
	176	"setup=setenv bootargs console=ttyS0,$baudrate " \
	177	"$mtdparts\0" \
	178	"setpart=" \
	179	"if test -n $swapos; then " \
	180	"setenv swapos; saveenv; " \
	181	"else " \
53677ef1 WD	182	"if test $ospart -eq 0; then setenv ospart 1;" \
53677ef1 WD	183	"else setenv ospart 0; fi; " \
f4e7cbfc PP	184	"fi\0" \
f4e7cbfc PP	185	"nfsargs=setenv bootargs $bootargs " \
53677ef1	186	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
f4e7cbfc PP	187	"nfsroot=$rootpath root=/dev/nfs\0" \
	188	"flashargs=run setpart;setenv bootargs $bootargs " \
	189	"root=mtd:rootfs$ospart ro " \
	190	"rootfstype=jffs2\0" \
53677ef1	191	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
f4e7cbfc PP	192	"fboot=run flashargs;nboot kernel$ospart\0" \
f4e7cbfc PP	193	"nboot=bootp;run nfsargs;tftp\0"
ac7eb8a3 WD	194
	195	#if 0 /* feel free to disable for development */
	196	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
f2302d44 SR	197	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	198	"\nNetStar PBX - boot in %d secs...\n", bootdelay
f4e7cbfc	199	#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
ac7eb8a3 WD	200	#endif
	201
	202	/*
	203	* Miscellaneous configurable options
	204	*/
6d0f6bcf JCPV	205	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	206	#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */
	207	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	208	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	209	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	210	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	211
	212	#define CONFIG_SYS_HUSH_PARSER
	213	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
ac7eb8a3 WD	214	#define CONFIG_AUTO_COMPLETE
ac7eb8a3 WD	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	217	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
	218	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
ac7eb8a3	219
6d0f6bcf	220	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
ac7eb8a3	221
6d0f6bcf	222	#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
ac7eb8a3 WD	223
	224	/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
	225	* This time is further subdivided by a local divisor.
	226	*/
6d0f6bcf JCPV	227	#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
	228	#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
	229	#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
ac7eb8a3 WD	230
	231	#define OMAP5910_DPLL_DIV 1
	232	#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
	233	(1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
	234
	235	#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
	236	#define OMAP5910_LCD_DIV 2 /* CKL/4 */
	237	#define OMAP5910_ARM_DIV 0 /* CKL/1 */
	238	#define OMAP5910_DSP_DIV 0 /* CKL/1 */
	239	#define OMAP5910_TC_DIV 1 /* CKL/2 */
	240	#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
	241	#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
	242
	243	#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
	244	#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) \| \
	245	(OMAP5910_LCD_DIV << 2) \| \
	246	(OMAP5910_ARM_DIV << 4) \| \
	247	(OMAP5910_DSP_DIV << 6) \| \
	248	(OMAP5910_TC_DIV << 8) \| \
	249	(OMAP5910_DSP_MMU_DIV << 10) \| \
	250	(OMAP5910_ARM_TIM_SEL << 12))
	251
	252	#endif /* __CONFIG_H */