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1 | /* |
2 | * Copyright (C) 2004 by FS Forth-Systeme GmbH. | |
3 | * All rights reserved. | |
4 | * Markus Pietrek <mpietrek@fsforth.de> | |
5 | * | |
6 | * Configuation settings for the NetSilicon NS9750 DevBoard | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
80885a9d WD |
30 | /* |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ | |
35 | #define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ | |
36 | #define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ | |
37 | ||
38 | /* input clock of PLL */ | |
39 | #define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ | |
40 | ||
41 | #define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) | |
42 | #define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) | |
43 | #define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) | |
44 | ||
45 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
46 | /*@TODO #define CONFIG_STATUS_LED*/ | |
47 | #define CONFIG_USE_IRQ | |
48 | ||
49 | /* | |
50 | * Size of malloc() pool | |
51 | */ | |
52 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) | |
53 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial | |
54 | * data */ | |
55 | ||
56 | /* | |
57 | * Hardware drivers | |
58 | */ | |
59 | #define CFG_NS9750_UART 1 /* use on-chip UART */ | |
60 | #define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */ | |
61 | ||
62 | /* | |
63 | * select serial console configuration | |
64 | */ | |
65 | #define CONFIG_CONS_INDEX 1 /* Port B */ | |
66 | ||
67 | /* allow to overwrite serial and ethaddr */ | |
68 | #define CONFIG_ENV_OVERWRITE | |
69 | ||
70 | #define CONFIG_BAUDRATE 38400 | |
71 | ||
72 | /*********************************************************** | |
73 | * Command definition | |
74 | ***********************************************************/ | |
75 | #if 0 /* @TODO */ | |
76 | #define CONFIG_COMMANDS \ | |
77 | (CONFIG_CMD_DFL | \ | |
78 | CFG_CMD_CACHE | \ | |
79 | /*CFG_CMD_NAND |*/ \ | |
80 | /*CFG_CMD_EEPROM |*/ \ | |
81 | /*CFG_CMD_I2C |*/ \ | |
82 | /*CFG_CMD_USB |*/ \ | |
83 | CFG_CMD_REGINFO | \ | |
84 | CFG_CMD_DATE | \ | |
85 | CFG_CMD_ELF) | |
86 | #else | |
87 | #define CONFIG_COMMANDS \ | |
88 | (CONFIG_CMD_BDI | \ | |
89 | CFG_CMD_NET | \ | |
90 | CFG_CMD_PING | \ | |
91 | CFG_CMD_CONSOLE | \ | |
92 | CFG_CMD_LOADB | \ | |
93 | CFG_CMD_LOADS | \ | |
94 | CFG_CMD_MEMORY) | |
95 | #endif | |
96 | ||
97 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
98 | #include <cmd_confdefs.h> | |
99 | ||
100 | #define CONFIG_BOOTDELAY 3 | |
101 | /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ | |
102 | ||
103 | #define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ | |
104 | #define CONFIG_NETMASK 255.255.255.0 | |
105 | #define CONFIG_IPADDR 192.168.42.30 | |
106 | #define CONFIG_SERVERIP 192.168.42.1 | |
107 | ||
108 | /*#define CONFIG_BOOTFILE "elinos-lart" */ | |
109 | /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ | |
110 | ||
111 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
112 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ | |
113 | /* what's this ? it's not used anywhere */ | |
114 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
115 | #endif | |
116 | ||
117 | /* | |
118 | * Miscellaneous configurable options | |
119 | */ | |
120 | #define CFG_LONGHELP /* undef to save memory */ | |
121 | #define CFG_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ | |
122 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
123 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
124 | #define CFG_MAXARGS 16 /* max number of command args */ | |
125 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
126 | ||
127 | #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ | |
128 | #define CFG_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ | |
129 | ||
130 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
131 | ||
132 | #define CFG_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ | |
133 | ||
134 | #define CFG_HZ (CPU_CLK_FREQ/64) | |
135 | ||
136 | /* valid baudrates */ | |
137 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
138 | ||
139 | #define NS9750_ETH_PHY_ADDRESS (0x0000) | |
140 | ||
141 | /*----------------------------------------------------------------------- | |
142 | * Stack sizes | |
143 | * | |
144 | * The stack sizes are set up in start.S using the settings below | |
145 | */ | |
146 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
147 | #ifdef CONFIG_USE_IRQ | |
148 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
149 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
150 | #endif | |
151 | ||
152 | /*----------------------------------------------------------------------- | |
153 | * Physical Memory Map | |
154 | */ | |
155 | /* TODO */ | |
156 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ | |
157 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
158 | #define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ | |
159 | #define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ | |
160 | #define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ | |
161 | ||
162 | #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ | |
163 | ||
164 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
165 | ||
166 | /*----------------------------------------------------------------------- | |
167 | * FLASH and environment organization | |
168 | */ | |
169 | ||
170 | /* @TODO*/ | |
171 | #define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ | |
172 | #if 0 | |
173 | #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ | |
174 | #endif | |
175 | ||
176 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
177 | #ifdef CONFIG_AMD_LV800 | |
178 | #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ | |
179 | #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ | |
180 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ | |
181 | #endif | |
182 | #ifdef CONFIG_AMD_LV400 | |
183 | #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ | |
184 | #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ | |
185 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ | |
186 | #endif | |
187 | ||
188 | /* timeout values are in ticks */ | |
189 | #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ | |
190 | #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ | |
191 | ||
192 | /* @TODO */ | |
193 | /*#define CFG_ENV_IS_IN_FLASH 1*/ | |
194 | #define CFG_ENV_IS_NOWHERE | |
195 | #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
196 | ||
197 | #ifdef CONFIG_STATUS_LED | |
198 | ||
199 | extern void __led_init(led_id_t mask, int state); | |
200 | extern void __led_toggle(led_id_t mask); | |
201 | extern void __led_set(led_id_t mask, int state); | |
202 | ||
203 | #endif /* CONFIG_STATUS_LED */ | |
204 | ||
205 | #endif /* __CONFIG_H */ |