[people/ms/u-boot.git] / include / configs / ns9750dev.h

/*
 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
 * All rights reserved.
 * Markus Pietrek <mpietrek@fsforth.de>
 *
 * Configuation settings for the NetSilicon NS9750 DevBoard
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */

/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */

#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
/*@TODO #define CONFIG_STATUS_LED*/
#define CONFIG_USE_IRQ

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
					 * data */

/*
 * Hardware drivers
 */
#define CONFIG_NS9750_UART		1	/* use on-chip UART */
#define CONFIG_DRIVER_NS9750_ETHERNET	1	/* use on-chip ethernet */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX          1		/* Port B */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	3
/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */

#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		192.168.42.30
#define CONFIG_SERVERIP		192.168.42.1

/*#define CONFIG_BOOTFILE	"elinos-lart" */
/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */

#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define	CONFIG_SYS_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */

#define	CONFIG_SYS_HZ			(CPU_CLK_FREQ/64)

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define NS9750_ETH_PHY_ADDRESS	(0x0000)

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
/* TODO */
#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */

#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* @TODO*/
#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
#if 0
#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
#endif

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* @TODO */
/*#define	CONFIG_ENV_IS_IN_FLASH	1*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */

#ifdef CONFIG_STATUS_LED

extern void __led_init(led_id_t mask, int state);
extern void __led_toggle(led_id_t mask);
extern void __led_set(led_id_t mask, int state);

#endif /* CONFIG_STATUS_LED */

#endif	/* __CONFIG_H */
Commit	Line	Data
80885a9d WD	1	/*
	2	* Copyright (C) 2004 by FS Forth-Systeme GmbH.
	3	* All rights reserved.
	4	* Markus Pietrek <mpietrek@fsforth.de>
	5	*
	6	* Configuation settings for the NetSilicon NS9750 DevBoard
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
80885a9d WD	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	35	#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
	36	#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
	37
	38	/* input clock of PLL */
	39	#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
	40
	41	#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
	42	#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
	43	#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
	44
	45	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	46	/@TODO #define CONFIG_STATUS_LED/
	47	#define CONFIG_USE_IRQ
	48
	49	/*
	50	* Size of malloc() pool
	51	*/
6d0f6bcf JCPV	52	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
6d0f6bcf JCPV	53	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
80885a9d WD	54	* data */
	55
	56	/*
	57	* Hardware drivers
	58	*/
1a6ffbfa	59	#define CONFIG_NS9750_UART 1 /* use on-chip UART */
80885a9d WD	60	#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */
	61
	62	/*
	63	* select serial console configuration
	64	*/
53677ef1	65	#define CONFIG_CONS_INDEX 1 /* Port B */
80885a9d WD	66
	67	/* allow to overwrite serial and ethaddr */
	68	#define CONFIG_ENV_OVERWRITE
	69
	70	#define CONFIG_BAUDRATE 38400
	71
929a2bfd	72
7f5c0157 JL	73	/*
	74	* BOOTP options
	75	*/
	76	#define CONFIG_BOOTP_BOOTFILESIZE
	77	#define CONFIG_BOOTP_BOOTPATH
	78	#define CONFIG_BOOTP_GATEWAY
	79	#define CONFIG_BOOTP_HOSTNAME
	80
	81
929a2bfd JL	82	/*
	83	* Command line configuration.
	84	*/
	85
	86	#define CONFIG_CMD_BDI
	87	#define CONFIG_CMD_CONSOLE
	88	#define CONFIG_CMD_LOADB
	89	#define CONFIG_CMD_LOADS
	90	#define CONFIG_CMD_MEMORY
	91	#define CONFIG_CMD_NET
	92	#define CONFIG_CMD_PING
	93
80885a9d WD	94
80885a9d WD	95	#define CONFIG_BOOTDELAY 3
53677ef1	96	/#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" /
80885a9d WD	97
	98	#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /@TODO unset /
	99	#define CONFIG_NETMASK 255.255.255.0
	100	#define CONFIG_IPADDR 192.168.42.30
	101	#define CONFIG_SERVERIP 192.168.42.1
	102
	103	/#define CONFIG_BOOTFILE "elinos-lart" /
	104	/#define CONFIG_BOOTCOMMAND "tftp; bootm" /
	105
929a2bfd	106	#if defined(CONFIG_CMD_KGDB)
80885a9d WD	107	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	108	/* what's this ? it's not used anywhere */
	109	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	110	#endif
	111
	112	/*
	113	* Miscellaneous configurable options
	114	*/
6d0f6bcf JCPV	115	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	116	#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
	117	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	118	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	119	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	120	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
80885a9d	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	123	#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM / / @TODO */
80885a9d	124
6d0f6bcf	125	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
80885a9d	126
6d0f6bcf	127	#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address / / @TODO */
80885a9d	128
6d0f6bcf	129	#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64)
80885a9d WD	130
80885a9d WD	131	/* valid baudrates */
6d0f6bcf	132	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
80885a9d WD	133
	134	#define NS9750_ETH_PHY_ADDRESS (0x0000)
	135
	136	/*-----------------------------------------------------------------------
	137	* Stack sizes
	138	*
	139	* The stack sizes are set up in start.S using the settings below
	140	*/
	141	#define CONFIG_STACKSIZE (1281024) / regular stack */
	142	#ifdef CONFIG_USE_IRQ
	143	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	144	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	145	#endif
	146
	147	/*-----------------------------------------------------------------------
	148	* Physical Memory Map
	149	*/
	150	/* TODO */
	151	#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
	152	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	153	#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
	154	#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
	155	#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
	156
	157	#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
	158
6d0f6bcf	159	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
80885a9d WD	160
	161	/*-----------------------------------------------------------------------
	162	* FLASH and environment organization
	163	*/
	164
	165	/* @TODO*/
	166	#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
	167	#if 0
	168	#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
	169	#endif
	170
6d0f6bcf	171	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
80885a9d WD	172	#ifdef CONFIG_AMD_LV800
80885a9d WD	173	#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
6d0f6bcf JCPV	174	#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
6d0f6bcf JCPV	175	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
80885a9d WD	176	#endif
	177	#ifdef CONFIG_AMD_LV400
	178	#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
6d0f6bcf JCPV	179	#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
6d0f6bcf JCPV	180	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
80885a9d WD	181	#endif
	182
	183	/* timeout values are in ticks */
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_ERASE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	185	#define CONFIG_SYS_FLASH_WRITE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Write */
80885a9d WD	186
80885a9d WD	187	/* @TODO */
5a1aceb0	188	/#define CONFIG_ENV_IS_IN_FLASH 1/
93f6d725	189	#define CONFIG_ENV_IS_NOWHERE
0e8d1586	190	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
80885a9d WD	191
	192	#ifdef CONFIG_STATUS_LED
	193
	194	extern void __led_init(led_id_t mask, int state);
	195	extern void __led_toggle(led_id_t mask);
	196	extern void __led_set(led_id_t mask, int state);
	197
	198	#endif /* CONFIG_STATUS_LED */
	199
	200	#endif /* __CONFIG_H */