[people/ms/u-boot.git] / include / configs / o2dnt-common.h

/*
 *  Common configuration options for ifm camera boards
 *
 * (C) Copyright 2005
 * Sebastien Cazaux, ifm electronic gmbh
 *
 * (C) Copyright 2012
 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __O2D_CONFIG_H
#define __O2D_CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5200

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
/* log base 2 of the above value */
#define CONFIG_SYS_CACHELINE_SHIFT	5
#endif

/*
#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY | \
			 CONFIG_SYS_POST_I2C)
*/

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI_PNP		1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

#define CONFIG_SYS_ALT_MEMTEST	/* Much more complex memory test */

/*
 * Supported commands
 */
#define CONFIG_CMD_EEPROM
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif

#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
/* Boot low with 16 or 32 MB Flash */
#define CONFIG_SYS_LOWBOOT	1
#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
#error "CONFIG_SYS_TEXT_BASE value is invalid"
#endif


#define CONFIG_PREBOOT	"run master"

#undef	CONFIG_BOOTARGS

#if !defined(CONSOLE_DEV)
#define CONSOLE_DEV	"ttyPSC1"
#endif

/*
 * Default environment for booting old and new kernel versions
 */
#define CONFIG_IFM_DEFAULT_ENV_OLD					\
	"flash_self_old=run ramargs addip addmem;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs_old=run nfsargs addip addmem;"			\
		"bootm ${kernel_addr}\0"				\
	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
		"run nfsargs addip addmem;"				\
		"bootm ${kernel_addr_r}\0"

#define CONFIG_IFM_DEFAULT_ENV_NEW					\
	"fdt_addr_r=900000\0"						\
	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"	\
	"flash_self=run ramargs addip addtty addmisc;"			\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmisc;"			\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addtty addmisc;"			\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\

#define	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
	"IOpin=0x64\0"							\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addmem=setenv bootargs ${bootargs} ${memlimit}\0"		\
	"addmisc=sete bootargs ${bootargs} ${miscargs}\0"		\
	"addtty=sete bootargs ${bootargs} console="			\
		CONSOLE_DEV ",${baudrate}\0"			\
	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"	\
	"kernel_addr_r=600000\0"					\
	"initrd_high=0x03e00000\0"					\
	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
	"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
		"cp.b ${fileaddr} ${linbot} ${filesize}\0"		\
	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"	\
		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"	\
	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"	\
		"cp.b ${fileaddr} ${jffbot} ${filesize}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"uboname=" CONFIG_BOARD_NAME					\
		"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"		\
	"progubo=tftp 200000 ${uboname};"				\
		"protect off ${ubobot} ${ubotop};"			\
		"erase ${ubobot} ${ubotop};"				\
		"cp.b ${fileaddr} ${ubobot} ${filesize}\0"		\
	"unlock=yes\0"							\
	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
		"setenv bootdelay 1;"					\
		"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "		\
			BOARD_POST_CRC32_END";"				\
		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"

#define CONFIG_BOOTCOMMAND	"run post"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration:
 *
 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 * organized as 2048 x 8 bits and addressable as eight I2C devices
 * 0x50 ... 0x57 each 256 bytes in size
 *
 */
#define CONFIG_SYS_I2C_FRAM
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
/*
 * There is no write delay with FRAM, write operations are performed at bus
 * speed. Thus, no status polling or write delay is needed.
 */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Write Timeout (in ms) */
/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
/* "Real" (hardware) sectors protection */
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE	0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
/* End of used area in DPRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10) /* 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial map for Linux */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR			0x00
#define CONFIG_RESET_PHY_R

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPIO_DATADIR		0x00000064 /* PSC1_2, PSC2_1,2 output */
#define CONFIG_SYS_GPIO_OPENDRAIN	0x00000000 /* No open drain */
#define CONFIG_SYS_GPIO_DATAVALUE	0x00000000 /* PSC1_1 to 1, rest to 0 */
#define CONFIG_SYS_GPIO_ENABLE		0x00000064 /* PSC1_2, PSC2_1,2 enable */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_CMDLINE_EDITING

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS		16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x100000

/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE		0x33333333

/*
 * DT support
 */
#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)

#endif /* __O2D_CONFIG_H */
Commit	Line	Data
4387cf1a AG	1	/*
	2	* Common configuration options for ifm camera boards
	3	*
	4	* (C) Copyright 2005
	5	* Sebastien Cazaux, ifm electronic gmbh
	6	*
	7	* (C) Copyright 2012
	8	* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
4387cf1a AG	11	*/
	12
	13	#ifndef __O2D_CONFIG_H
	14	#define __O2D_CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
4387cf1a AG	19	#define CONFIG_MPC5200
	20
	21	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
	22
	23	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	24	#if defined(CONFIG_CMD_KGDB)
	25	/* log base 2 of the above value */
	26	#define CONFIG_SYS_CACHELINE_SHIFT 5
	27	#endif
	28
	29	/*
	30	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	31	CONFIG_SYS_POST_I2C)
	32	*/
	33
	34	#ifdef CONFIG_POST
	35	/* preserve space for the post_word at end of on-chip SRAM */
	36	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
	37	#endif
	38
	39	/*
	40	* Serial console configuration
	41	*/
	42	#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
	43	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	44	#define CONFIG_SYS_BAUDRATE_TABLE \
	45	{ 9600, 19200, 38400, 57600, 115200, 230400 }
	46
	47	/*
	48	* PCI Mapping:
	49	* 0x40000000 - 0x4fffffff - PCI Memory
	50	* 0x50000000 - 0x50ffffff - PCI IO Space
	51	*/
4387cf1a AG	52	#define CONFIG_PCI_PNP 1
	53
	54	#define CONFIG_PCI_MEM_BUS 0x40000000
	55	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	56	#define CONFIG_PCI_MEM_SIZE 0x10000000
	57
	58	#define CONFIG_PCI_IO_BUS 0x50000000
	59	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	60	#define CONFIG_PCI_IO_SIZE 0x01000000
	61
	62	#define CONFIG_SYS_XLB_PIPELINING 1
	63
	64	/* Partitions */
	65	#define CONFIG_MAC_PARTITION
	66	#define CONFIG_DOS_PARTITION
	67	#define CONFIG_ISO_PARTITION
	68
	69	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	70
	71	#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
	72
	73	/*
	74	* Supported commands
	75	*/
4387cf1a	76	#define CONFIG_CMD_EEPROM
4387cf1a AG	77	#ifdef CONFIG_PCI
	78	#define CONFIG_CMD_PCI
	79	#endif
	80	#ifdef CONFIG_POST
	81	#define CONFIG_CMD_DIAG
	82	#endif
	83
	84	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) \|\| (CONFIG_SYS_TEXT_BASE == 0xFF000000)
	85	/* Boot low with 16 or 32 MB Flash */
	86	#define CONFIG_SYS_LOWBOOT 1
	87	#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
	88	#error "CONFIG_SYS_TEXT_BASE value is invalid"
	89	#endif
	90
4387cf1a AG	91
	92	#define CONFIG_PREBOOT "run master"
	93
	94	#undef CONFIG_BOOTARGS
	95
12ca05a3 SG	96	#if !defined(CONSOLE_DEV)
12ca05a3 SG	97	#define CONSOLE_DEV "ttyPSC1"
4387cf1a AG	98	#endif
	99
	100	/*
	101	* Default environment for booting old and new kernel versions
	102	*/
	103	#define CONFIG_IFM_DEFAULT_ENV_OLD \
	104	"flash_self_old=run ramargs addip addmem;" \
	105	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	106	"flash_nfs_old=run nfsargs addip addmem;" \
	107	"bootm ${kernel_addr}\0" \
	108	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
	109	"run nfsargs addip addmem;" \
	110	"bootm ${kernel_addr_r}\0"
	111
	112	#define CONFIG_IFM_DEFAULT_ENV_NEW \
	113	"fdt_addr_r=900000\0" \
	114	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
	115	"flash_self=run ramargs addip addtty addmisc;" \
	116	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	117	"flash_nfs=run nfsargs addip addtty addmisc;" \
	118	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	119	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	120	"tftp ${fdt_addr_r} ${fdt_file}; " \
	121	"run nfsargs addip addtty addmisc;" \
	122	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	123
	124	#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
	125	"IOpin=0x64\0" \
	126	"addip=setenv bootargs ${bootargs} " \
	127	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	128	":${hostname}:${netdev}:off panic=1\0" \
	129	"addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
	130	"addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
	131	"addtty=sete bootargs ${bootargs} console=" \
12ca05a3	132	CONSOLE_DEV ",${baudrate}\0" \
4387cf1a AG	133	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
	134	"kernel_addr_r=600000\0" \
	135	"initrd_high=0x03e00000\0" \
	136	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
4a8c3f69	137	"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
4387cf1a AG	138	"netdev=eth0\0" \
	139	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	140	"nfsroot=${serverip}:${rootpath}\0" \
	141	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	142	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
	143	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
	144	"cp.b ${fileaddr} ${linbot} ${filesize}\0" \
	145	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
	146	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
	147	"cp.b ${fileaddr} ${rambot} ${filesize}\0" \
	148	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
	149	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
	150	"cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
	151	"rootpath=/opt/eldk/ppc_6xx\0" \
	152	"uboname=" CONFIG_BOARD_NAME \
	153	"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
	154	"progubo=tftp 200000 ${uboname};" \
	155	"protect off ${ubobot} ${ubotop};" \
	156	"erase ${ubobot} ${ubotop};" \
	157	"cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
	158	"unlock=yes\0" \
	159	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
	160	"setenv bootdelay 1;" \
4a8c3f69	161	"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
4387cf1a AG	162	BOARD_POST_CRC32_END";" \
	163	"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
	164
	165	#define CONFIG_BOOTCOMMAND "run post"
	166
	167	/*
	168	* IPB Bus clocking configuration.
	169	*/
	170	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	171
	172	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
	173	/*
	174	* PCI Bus clocking configuration
	175	*
	176	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
	177	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
	178	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
	179	*/
	180	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
	181	#endif
	182
	183	/*
	184	* I2C configuration
	185	*/
	186	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	187	#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
	188	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	189	#define CONFIG_SYS_I2C_SLAVE 0x7F
	190
	191	/*
	192	* EEPROM configuration:
	193	*
	194	* O2DNT board is equiped with Ramtron FRAM device FM24CL16
	195	* 16 Kib Ferroelectric Nonvolatile serial RAM memory
	196	* organized as 2048 x 8 bits and addressable as eight I2C devices
	197	* 0x50 ... 0x57 each 256 bytes in size
	198	*
	199	*/
	200	#define CONFIG_SYS_I2C_FRAM
	201	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	202	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	203	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	204	/*
	205	* There is no write delay with FRAM, write operations are performed at bus
	206	* speed. Thus, no status polling or write delay is needed.
	207	*/
	208
	209	/*
	210	* Flash configuration
	211	*/
	212	#define CONFIG_SYS_FLASH_CFI 1
	213	#define CONFIG_FLASH_CFI_DRIVER 1
	214	#define CONFIG_FLASH_16BIT
	215	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	216	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
	217	#define CONFIG_SYS_FLASH_EMPTY_INFO
	218
	219	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	220	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	221	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
	222	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
	223	/* Timeout for Flash Clear Lock Bits (in ms) */
	224	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
	225	/* "Real" (hardware) sectors protection */
226	#define CONFIG_SYS_FLASH_PROTECTION
227
228	/*
229	* Environment settings
230	*/
231	#define CONFIG_ENV_IS_IN_FLASH 1
232	#define CONFIG_ENV_SIZE 0x20000
233	#define CONFIG_ENV_SECT_SIZE 0x20000
234	#define CONFIG_ENV_OVERWRITE 1
235	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
236
237	/*
238	* Memory map
239	*/
240	#define CONFIG_SYS_MBAR 0xF0000000
241	#define CONFIG_SYS_SDRAM_BASE 0x00000000
242	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
243
244	/* Use SRAM until RAM will be available */
245	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
246	#ifdef CONFIG_POST
247	/* preserve space for the post_word at end of on-chip SRAM */
b39d1213	248	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
4387cf1a AG	249	#else
4387cf1a AG	250	/* End of used area in DPRAM */
b39d1213	251	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
4387cf1a AG	252	#endif
4387cf1a AG	253
b39d1213	254	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
627b73e2	255	GENERATED_GBL_DATA_SIZE)
4387cf1a AG	256	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	257
	258	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	259	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
	260	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
	261	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
	262
	263	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	264	#define CONFIG_SYS_RAMBOOT 1
	265	#endif
	266
	267	/*
	268	* Ethernet configuration
	269	*/
	270	#define CONFIG_MPC5xxx_FEC
	271	#define CONFIG_MPC5xxx_FEC_MII100
	272	#define CONFIG_PHY_ADDR 0x00
	273	#define CONFIG_RESET_PHY_R
	274
	275	/*
	276	* GPIO configuration
	277	*/
	278	#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
	279	#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
	280	#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
	281	#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
	282
	283	/*
	284	* Miscellaneous configurable options
	285	*/
	286	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4387cf1a	287	#define CONFIG_CMDLINE_EDITING
4387cf1a AG	288
	289	#if defined(CONFIG_CMD_KGDB)
	290	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	291	#else
	292	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	293	#endif
	294	/* Print Buffer Size */
	295	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	296	sizeof(CONFIG_SYS_PROMPT) + 16)
	297	/* max number of command args */
	298	#define CONFIG_SYS_MAXARGS 16
	299	/* Boot Argument Buffer Size */
	300	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	301
	302	/* default load address */
	303	#define CONFIG_SYS_LOAD_ADDR 0x100000
	304
	305	/* decrementer freq: 1 ms ticks */
4387cf1a AG	306
	307	/*
	308	* Various low-level settings
	309	*/
	310	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	311	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	312
	313	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	314	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	315	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	316	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	317
	318	#define CONFIG_BOARD_EARLY_INIT_R
	319
	320	#define CONFIG_SYS_CS_BURST 0x00000000
	321	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
	322
	323	/*
	324	* DT support
	325	*/
4387cf1a AG	326	#define OF_CPU "PowerPC,5200@0"
	327	#define OF_SOC "soc5200@f0000000"
	328	#define OF_TBCLK (bd->bi_busfreq / 4)
	329
	330	#endif /* __O2D_CONFIG_H */