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1/*
2 * Copyright (C) 2014 Samsung Electronics
3 * Sanghee Kim <sh0130.kim@samsung.com>
4 * Piotr Wilczek <p.wilczek@samsung.com>
5 * Przemyslaw Marczak <p.marczak@samsung.com>
6 *
7 * Configuation settings for the Odroid-U3 (EXYNOS4412) board.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef __CONFIG_ODROID_U3_H
13#define __CONFIG_ODROID_U3_H
14
4c7bb1d2 15#include <configs/exynos4-common.h>
73eca211 16
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17#define CONFIG_SYS_L2CACHE_OFF
18#ifndef CONFIG_SYS_L2CACHE_OFF
19#define CONFIG_SYS_L2_PL310
20#define CONFIG_SYS_PL310_BASE 0x10502000
21#endif
22
23#define CONFIG_MACH_TYPE 4289
24
25#define CONFIG_NR_DRAM_BANKS 8
26#define CONFIG_SYS_SDRAM_BASE 0x40000000
27#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
28#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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29/* Reserve the last 1 MiB for the secure firmware */
30#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL)
31#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
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32
33/* memtest works on */
34#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
35#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
36#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
37#define CONFIG_SYS_TEXT_BASE 0x43e00000
38
39#include <linux/sizes.h>
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40
41/* select serial console configuration */
42#define CONFIG_SERIAL1
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43
44/* Console configuration */
73eca211 45
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46#define CONFIG_BOOTARGS "Please use defined boot"
47#define CONFIG_BOOTCOMMAND "run autoboot"
48#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
49
50#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
51 - GENERATED_GBL_DATA_SIZE)
52
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53#define CONFIG_SYS_MONITOR_BASE 0x00000000
54
55#define CONFIG_ENV_IS_IN_MMC
56#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
57#define CONFIG_ENV_SIZE 4096
58#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
59#define CONFIG_ENV_OVERWRITE
60
61/* Partitions name */
62#define PARTS_BOOT "boot"
63#define PARTS_ROOT "platform"
64
65#define CONFIG_DFU_ALT \
66 "uImage fat 0 1;" \
67 "zImage fat 0 1;" \
68 "Image.itb fat 0 1;" \
69 "uInitrd fat 0 1;" \
70 "exynos4412-odroidu3.dtb fat 0 1;" \
71 "exynos4412-odroidx2.dtb fat 0 1;" \
72 ""PARTS_BOOT" part 0 1;" \
73 ""PARTS_ROOT" part 0 2\0" \
74
75#define CONFIG_SET_DFU_ALT_INFO
76#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
77
78#define CONFIG_DFU_ALT_BOOT_EMMC \
79 "u-boot raw 0x3e 0x800 mmcpart 1;" \
80 "bl1 raw 0x0 0x1e mmcpart 1;" \
81 "bl2 raw 0x1e 0x1d mmcpart 1;" \
82 "tzsw raw 0x83e 0x138 mmcpart 1\0"
83
84#define CONFIG_DFU_ALT_BOOT_SD \
85 "u-boot raw 0x3f 0x800;" \
86 "bl1 raw 0x1 0x1e;" \
87 "bl2 raw 0x1f 0x1d;" \
88 "tzsw raw 0x83f 0x138\0"
89
90/*
91 * Bootable media layout:
92 * dev: SD eMMC(part boot)
93 * BL1 1 0
94 * BL2 31 30
95 * UBOOT 63 62
96 * TZSW 2111 2110
97 * ENV 2560 2560(part user)
98 *
99 * MBR Primary partiions:
100 * Num Name Size Offset
101 * 1. BOOT: 100MiB 2MiB
102 * 2. ROOT: -
103*/
104#define CONFIG_EXTRA_ENV_SETTINGS \
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105 "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \
106 "boot.scr\0" \
4ed50807 107 "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
73eca211 108 "${kernelname}\0" \
4ed50807 109 "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
73eca211 110 "${initrdname}\0" \
4ed50807 111 "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
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112 "${fdtfile}\0" \
113 "check_ramdisk=" \
114 "if run loadinitrd; then " \
115 "setenv initrd_addr ${initrdaddr};" \
116 "else " \
117 "setenv initrd_addr -;" \
118 "fi;\0" \
119 "check_dtb=" \
120 "if run loaddtb; then " \
121 "setenv fdt_addr ${fdtaddr};" \
122 "else " \
123 "setenv fdt_addr;" \
124 "fi;\0" \
125 "kernel_args=" \
126 "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
127 " rootwait ${console} ${opts}\0" \
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128 "boot_script=" \
129 "run loadbootscript;" \
130 "source ${scriptaddr}\0" \
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131 "boot_fit=" \
132 "setenv kerneladdr 0x42000000;" \
133 "setenv kernelname Image.itb;" \
134 "run loadkernel;" \
135 "run kernel_args;" \
136 "bootm ${kerneladdr}#${boardname}\0" \
137 "boot_uimg=" \
138 "setenv kerneladdr 0x40007FC0;" \
139 "setenv kernelname uImage;" \
140 "run check_dtb;" \
141 "run check_ramdisk;" \
142 "run loadkernel;" \
143 "run kernel_args;" \
144 "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
145 "boot_zimg=" \
146 "setenv kerneladdr 0x40007FC0;" \
147 "setenv kernelname zImage;" \
148 "run check_dtb;" \
149 "run check_ramdisk;" \
150 "run loadkernel;" \
151 "run kernel_args;" \
152 "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
153 "autoboot=" \
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154 "if test -e mmc 0 boot.scr; then; " \
155 "run boot_script; " \
156 "elif test -e mmc 0 Image.itb; then; " \
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157 "run boot_fit;" \
158 "elif test -e mmc 0 zImage; then; " \
159 "run boot_zimg;" \
160 "elif test -e mmc 0 uImage; then; " \
161 "run boot_uimg;" \
162 "fi;\0" \
163 "console=" CONFIG_DEFAULT_CONSOLE \
164 "mmcbootdev=0\0" \
165 "mmcbootpart=1\0" \
166 "mmcrootdev=0\0" \
167 "mmcrootpart=2\0" \
168 "bootdelay=0\0" \
169 "dfu_alt_system="CONFIG_DFU_ALT \
170 "dfu_alt_info=Please reset the board\0" \
171 "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
172 "consoleoff=set console console=ram; save; reset\0" \
173 "initrdname=uInitrd\0" \
174 "initrdaddr=42000000\0" \
8e34a74d 175 "scriptaddr=0x42000000\0" \
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176 "fdtaddr=40800000\0"
177
178/* I2C */
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179#define CONFIG_SYS_I2C_S3C24X0
180#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
181#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
73eca211 182
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183/* GPT */
184#define CONFIG_RANDOM_UUID
185
186/* Security subsystem - enable hw_rand() */
187#define CONFIG_EXYNOS_ACE_SHA
188#define CONFIG_LIB_HW_RAND
189
6a23c653 190/* USB */
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191#define CONFIG_USB_EHCI
192#define CONFIG_USB_EHCI_EXYNOS
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193
194#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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195#define CONFIG_USB_HOST_ETHER
196#define CONFIG_USB_ETHER_SMSC95XX
197
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198/*
199 * Supported Odroid boards: X3, U3
200 * TODO: Add Odroid X support
201 */
202#define CONFIG_MISC_COMMON
203#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
204#define CONFIG_BOARD_TYPES
205#define CONFIG_MISC_INIT_R
206
207#undef CONFIG_REVISION_TAG
208
209#endif /* __CONFIG_H */