[people/ms/u-boot.git] / include / configs / omap3_cairo.h

/*
 * Configuration settings for the QUIPOS Cairo board.
 *
 * Copyright (C) DENX GmbH
 *
 * Author :
 *	Albert ARIBAUD <albert.aribaud@3adev.fr>
 *
 * Derived from EVM  code by
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Itself derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Also derived from include/configs/omap3_beagle.h
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __OMAP3_CAIRO_CONFIG_H
#define __OMAP3_CAIRO_CONFIG_H

#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.  We use this rather than the inherited defines from
 * ti_armv7_common.h for backwards compatibility.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#define CONFIG_NAND

#include <configs/ti_omap3_common.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

#define CONFIG_MISC_INIT_R

#define CONFIG_REVISION_TAG		1
#define CONFIG_ENV_OVERWRITE

/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS		1

/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }

#define CONFIG_NAND

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_NAND_LOCK_UNLOCK

/* Disable some commands */
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/

/*
 * TWL4030
 */
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
/* override default CONFIG_BOOTDELAY */
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY	0

#define CONFIG_EXTRA_ENV_SETTINGS \
	"machid=ffffffff\0" \
	"fdt_high=0x87000000\0" \
	"baudrate=115200\0" \
	"fec_addr=00:50:C2:7E:90:F0\0" \
	"netmask=255.255.255.0\0" \
	"ipaddr=192.168.2.9\0" \
	"gateway=192.168.2.1\0" \
	"serverip=192.168.2.10\0" \
	"nfshost=192.168.2.10\0" \
	"stdin=serial\0" \
	"stdout=serial\0" \
	"stderr=serial\0" \
	"bootargs_mmc_ramdisk=mem=128M " \
		"console=ttyO1,115200n8 " \
		"root=/dev/ram0 rw " \
		"initrd=0x81600000,16M " \
		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
	"mmcboot=mmc init; " \
		"fatload mmc 0 0x80000000 uImage; " \
		"fatload mmc 0 0x81600000 ramdisk.gz; " \
		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
		"bootm 0x80000000\0" \
	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
	"root=/dev/nfs " \
	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
	"omap_vout.vid1_static_vrfb_alloc=y\0" \
	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
	"bootm 0x80000000\0" \
	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
	"omapfb.rotate_type=1\0" \
	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
		"nand erase 0 20000; " \
		"fatload mmc 0 0x81600000 MLO; " \
		"nandecc hw; " \
		"nand write.i 0x81600000 0 20000;\0" \
	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
		"nand erase 80000 40000; " \
		"fatload mmc 0 0x81600000 u-boot.bin; " \
		"nandecc sw; " \
		"nand write.i 0x81600000 80000 40000;\0" \
	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
		"nand erase 280000 300000; " \
		"fatload mmc 0 0x81600000 uImage; " \
		"nandecc sw; " \
		"nand write.i 0x81600000 280000 300000;\0" \
	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
		"nandecc sw; " \
		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
		"nand erase 680000 ${filesize}; " \
		"nand write.jffs2 81600000 680000 ${filesize};\0" \
	"flash_scrub=nand scrub; " \
		"run flash_xloader; " \
		"run flash_uboot; " \
		"run flash_kernel; " \
		"run flash_rootfs;\0" \
	"flash_all=run ledred; " \
		"nand erase.chip; " \
		"run ledorange; " \
		"run flash_xloader; " \
		"run flash_uboot; " \
		"run flash_kernel; " \
		"run flash_rootfs; " \
		"run ledgreen; " \
		"run boot_nand; \0" \

#define CONFIG_BOOTCOMMAND \
	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
	"else run boot_nand; fi"

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_OMAP3_SPI

#define CONFIG_SYS_CACHELINE_SIZE	64

/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS		0x240000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
#endif

/* env defaults */
#define CONFIG_BOOTFILE			"uImage"

/* Override OMAP3 common serial console configuration from UART3
 * to UART2.
 *
 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
 * are needed and peripheral clocks for UART2 must be enabled in
 * function per_clocks_enable().
 */
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX		2
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SYS_NS16550_COM3
#define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
#undef CONFIG_SERIAL3
#define CONFIG_SERIAL2
#endif

/* Keep old prompt in case some existing script depends on it */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT		"Cairo # "

/* Provide MACH_TYPE for compatibility with non-DT kernels */
#define MACH_TYPE_OMAP3_CAIRO	3063
#define CONFIG_MACH_TYPE	MACH_TYPE_OMAP3_CAIRO

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#endif /* __OMAP3_CAIRO_CONFIG_H */
Commit	Line	Data
d275c40c AA	1	/*
	2	* Configuration settings for the QUIPOS Cairo board.
	3	*
	4	* Copyright (C) DENX GmbH
	5	*
	6	* Author :
	7	* Albert ARIBAUD <albert.aribaud@3adev.fr>
	8	*
	9	* Derived from EVM code by
	10	* Manikandan Pillai <mani.pillai@ti.com>
	11	* Itself derived from Beagle Board and 3430 SDP code by
	12	* Richard Woodruff <r-woodruff2@ti.com>
	13	* Syed Mohammed Khasim <khasim@ti.com>
	14	*
	15	* Also derived from include/configs/omap3_beagle.h
	16	*
	17	* SPDX-License-Identifier: GPL-2.0+
	18	*/
	19
	20	#ifndef __OMAP3_CAIRO_CONFIG_H
	21	#define __OMAP3_CAIRO_CONFIG_H
	22
	23	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	24
	25	/*
	26	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	27	* 64 bytes before this address should be set aside for u-boot.img's
	28	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	29	* other needs. We use this rather than the inherited defines from
	30	* ti_armv7_common.h for backwards compatibility.
	31	*/
	32	#define CONFIG_SYS_TEXT_BASE 0x80100000
	33	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	34	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	35	#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
	36	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	37	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	38
	39	#define CONFIG_NAND
	40
	41	#include <configs/ti_omap3_common.h>
	42
	43	/*
	44	* Display CPU and Board information
	45	*/
	46	#define CONFIG_DISPLAY_CPUINFO 1
	47	#define CONFIG_DISPLAY_BOARDINFO 1
	48
	49	#define CONFIG_MISC_INIT_R
	50
	51	#define CONFIG_REVISION_TAG 1
	52	#define CONFIG_ENV_OVERWRITE
	53
	54	/* Enable Multi Bus support for I2C */
	55	#define CONFIG_I2C_MULTI_BUS 1
	56
	57	/* Probe all devices */
	58	#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
	59
	60	#define CONFIG_NAND
	61
	62	/* commands to include */
	63	#include <config_cmd_default.h>
	64
d275c40c AA	65	#define CONFIG_CMD_NAND_LOCK_UNLOCK
	66
	67	/* Disable some commands */
	68	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	69	#undef CONFIG_CMD_IMI /* iminfo */
	70	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	71
	72	/*
	73	* TWL4030
	74	*/
	75	#define CONFIG_TWL4030_LED 1
	76
	77	/*
	78	* Board NAND Info.
	79	*/
	80	#define CONFIG_SYS_NAND_QUIET_TEST 1
	81	#define CONFIG_NAND_OMAP_GPMC
	82	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	83	/* devices */
	84	/* override default CONFIG_BOOTDELAY */
	85	#undef CONFIG_BOOTDELAY
	86	#define CONFIG_BOOTDELAY 0
	87
	88	#define CONFIG_EXTRA_ENV_SETTINGS \
	89	"machid=ffffffff\0" \
	90	"fdt_high=0x87000000\0" \
	91	"baudrate=115200\0" \
d275c40c AA	92	"fec_addr=00:50:C2:7E:90:F0\0" \
	93	"netmask=255.255.255.0\0" \
	94	"ipaddr=192.168.2.9\0" \
	95	"gateway=192.168.2.1\0" \
	96	"serverip=192.168.2.10\0" \
	97	"nfshost=192.168.2.10\0" \
	98	"stdin=serial\0" \
	99	"stdout=serial\0" \
	100	"stderr=serial\0" \
	101	"bootargs_mmc_ramdisk=mem=128M " \
	102	"console=ttyO1,115200n8 " \
	103	"root=/dev/ram0 rw " \
	104	"initrd=0x81600000,16M " \
	105	"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
	106	"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
	107	"mmcboot=mmc init; " \
	108	"fatload mmc 0 0x80000000 uImage; " \
	109	"fatload mmc 0 0x81600000 ramdisk.gz; " \
	110	"setenv bootargs ${bootargs_mmc_ramdisk}; " \
	111	"bootm 0x80000000\0" \
	112	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
	113	"root=/dev/nfs " \
	114	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
	115	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
	116	"omap_vout.vid1_static_vrfb_alloc=y\0" \
	117	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
	118	"bootm 0x80000000\0" \
	119	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
	120	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
	121	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
	122	"omapfb.rotate_type=1\0" \
	123	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
	124	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
	125	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	126	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	127	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
	128	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	129	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
	130	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
	131	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	132	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	133	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
	134	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	135	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	136	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
	137	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
	138	"nand erase 0 20000; " \
	139	"fatload mmc 0 0x81600000 MLO; " \
	140	"nandecc hw; " \
	141	"nand write.i 0x81600000 0 20000;\0" \
	142	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
	143	"nand erase 80000 40000; " \
	144	"fatload mmc 0 0x81600000 u-boot.bin; " \
	145	"nandecc sw; " \
	146	"nand write.i 0x81600000 80000 40000;\0" \
	147	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
	148	"nand erase 280000 300000; " \
	149	"fatload mmc 0 0x81600000 uImage; " \
	150	"nandecc sw; " \
	151	"nand write.i 0x81600000 280000 300000;\0" \
	152	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
	153	"nandecc sw; " \
	154	"nand write.jffs2 0x680000 0xFF ${filesize}; " \
	155	"nand erase 680000 ${filesize}; " \
156	"nand write.jffs2 81600000 680000 ${filesize};\0" \
157	"flash_scrub=nand scrub; " \
158	"run flash_xloader; " \
159	"run flash_uboot; " \
160	"run flash_kernel; " \
161	"run flash_rootfs;\0" \
162	"flash_all=run ledred; " \
163	"nand erase.chip; " \
164	"run ledorange; " \
165	"run flash_xloader; " \
166	"run flash_uboot; " \
167	"run flash_kernel; " \
168	"run flash_rootfs; " \
169	"run ledgreen; " \
170	"run boot_nand; \0" \
171
172	#define CONFIG_BOOTCOMMAND \
173	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
174	"else run boot_nand; fi"
175
176	/*
177	* OMAP3 has 12 GP timers, they can be driven by the system clock
178	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
179	* This rate is divided by a local divisor.
180	*/
181	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
182
183	/*-----------------------------------------------------------------------
184	* FLASH and environment organization
185	*/
186
187	/* ** PISMO SUPPORT * */
188	#if defined(CONFIG_CMD_NAND)
189	#define CONFIG_SYS_FLASH_BASE NAND_BASE
190	#endif
191
192	/* Monitor at start of flash */
193	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
194	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
195
196	#define CONFIG_ENV_IS_IN_NAND 1
197	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
198	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
199	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
200
201	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
202	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
203	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
204
205	#define CONFIG_OMAP3_SPI
206
207	#define CONFIG_SYS_CACHELINE_SIZE 64
208
209	/* Defines for SPL */
210	#define CONFIG_SPL_OMAP3_ID_NAND
211
212	/* NAND boot config */
213	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
214	#define CONFIG_SYS_NAND_PAGE_COUNT 64
215	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
216	#define CONFIG_SYS_NAND_OOBSIZE 64
217	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
218	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
219	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
220	10, 11, 12, 13}
221	#define CONFIG_SYS_NAND_ECCSIZE 512
222	#define CONFIG_SYS_NAND_ECCBYTES 3
223	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
224	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
225	/* NAND: SPL falcon mode configs */
226	#ifdef CONFIG_SPL_OS_BOOT
227	#define CONFIG_CMD_SPL_NAND_OFS 0x240000
228	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
229	#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
230	#endif
231
232	/* env defaults */
233	#define CONFIG_BOOTFILE "uImage"
234
235	/* Override OMAP3 common serial console configuration from UART3
236	* to UART2.
237	*
238	* Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
239	* are needed and peripheral clocks for UART2 must be enabled in
240	* function per_clocks_enable().
241	*/
242	#undef CONFIG_CONS_INDEX
243	#define CONFIG_CONS_INDEX 2
244	#ifdef CONFIG_SPL_BUILD
245	#undef CONFIG_SYS_NS16550_COM3
246	#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
247	#undef CONFIG_SERIAL3
248	#define CONFIG_SERIAL2
249	#endif
250
251	/* Keep old prompt in case some existing script depends on it */
252	#undef CONFIG_SYS_PROMPT
253	#define CONFIG_SYS_PROMPT "Cairo # "
254
255	/* Provide MACH_TYPE for compatibility with non-DT kernels */
256	#define MACH_TYPE_OMAP3_CAIRO 3063
257	#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
258
259	/*-----------------------------------------------------------------------
260	* FLASH and environment organization
261	*/
262
263	/* ** PISMO SUPPORT * */
264
265	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
266	/* on one chip */
267	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
268
269	/*-----------------------------------------------------------------------
270	* CFI FLASH driver setup
271	*/
272	/* timeout values are in ticks */
273	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
274	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
275
276	/* Flash banks JFFS2 should use */
277	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
278	CONFIG_SYS_MAX_NAND_DEVICE)
279	#define CONFIG_SYS_JFFS2_MEM_NAND
280	/* use flash_info[2] */
281	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
282	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
283
284	#endif /* __OMAP3_CAIRO_CONFIG_H */