[people/ms/u-boot.git] / include / configs / omap3_cairo.h

/*
 * Configuration settings for the QUIPOS Cairo board.
 *
 * Copyright (C) DENX GmbH
 *
 * Author :
 *	Albert ARIBAUD <albert.aribaud@3adev.fr>
 *
 * Derived from EVM  code by
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Itself derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Also derived from include/configs/omap3_beagle.h
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __OMAP3_CAIRO_CONFIG_H
#define __OMAP3_CAIRO_CONFIG_H

#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.  We use this rather than the inherited defines from
 * ti_armv7_common.h for backwards compatibility.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#define CONFIG_NAND

#include <configs/ti_omap3_common.h>

#define CONFIG_MISC_INIT_R

#define CONFIG_REVISION_TAG		1
#define CONFIG_ENV_OVERWRITE

/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS		1

/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }

#define CONFIG_NAND

/* commands to include */
#define CONFIG_CMD_NAND_LOCK_UNLOCK

/*
 * TWL4030
 */
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"machid=ffffffff\0" \
	"fdt_high=0x87000000\0" \
	"baudrate=115200\0" \
	"fec_addr=00:50:C2:7E:90:F0\0" \
	"netmask=255.255.255.0\0" \
	"ipaddr=192.168.2.9\0" \
	"gateway=192.168.2.1\0" \
	"serverip=192.168.2.10\0" \
	"nfshost=192.168.2.10\0" \
	"stdin=serial\0" \
	"stdout=serial\0" \
	"stderr=serial\0" \
	"bootargs_mmc_ramdisk=mem=128M " \
		"console=ttyO1,115200n8 " \
		"root=/dev/ram0 rw " \
		"initrd=0x81600000,16M " \
		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
	"mmcboot=mmc init; " \
		"fatload mmc 0 0x80000000 uImage; " \
		"fatload mmc 0 0x81600000 ramdisk.gz; " \
		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
		"bootm 0x80000000\0" \
	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
	"root=/dev/nfs " \
	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
	"omap_vout.vid1_static_vrfb_alloc=y\0" \
	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
	"bootm 0x80000000\0" \
	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
	"omapfb.rotate_type=1\0" \
	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
		"nand erase 0 20000; " \
		"fatload mmc 0 0x81600000 MLO; " \
		"nandecc hw; " \
		"nand write.i 0x81600000 0 20000;\0" \
	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
		"nand erase 80000 40000; " \
		"fatload mmc 0 0x81600000 u-boot.bin; " \
		"nandecc sw; " \
		"nand write.i 0x81600000 80000 40000;\0" \
	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
		"nand erase 280000 300000; " \
		"fatload mmc 0 0x81600000 uImage; " \
		"nandecc sw; " \
		"nand write.i 0x81600000 280000 300000;\0" \
	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
		"nandecc sw; " \
		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
		"nand erase 680000 ${filesize}; " \
		"nand write.jffs2 81600000 680000 ${filesize};\0" \
	"flash_scrub=nand scrub; " \
		"run flash_xloader; " \
		"run flash_uboot; " \
		"run flash_kernel; " \
		"run flash_rootfs;\0" \
	"flash_all=run ledred; " \
		"nand erase.chip; " \
		"run ledorange; " \
		"run flash_xloader; " \
		"run flash_uboot; " \
		"run flash_kernel; " \
		"run flash_rootfs; " \
		"run ledgreen; " \
		"run boot_nand; \0" \

#define CONFIG_BOOTCOMMAND \
	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
	"else run boot_nand; fi"

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_OMAP3_SPI

/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS		0x240000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
#endif

/* env defaults */
#define CONFIG_BOOTFILE			"uImage"

/* Override OMAP3 common serial console configuration from UART3
 * to UART2.
 *
 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
 * are needed and peripheral clocks for UART2 must be enabled in
 * function per_clocks_enable().
 */
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX		2
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SYS_NS16550_COM3
#define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
#undef CONFIG_SERIAL3
#define CONFIG_SERIAL2
#endif

/* Provide MACH_TYPE for compatibility with non-DT kernels */
#define MACH_TYPE_OMAP3_CAIRO	3063
#define CONFIG_MACH_TYPE	MACH_TYPE_OMAP3_CAIRO

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#endif /* __OMAP3_CAIRO_CONFIG_H */
Commit	Line	Data
d275c40c AA	1	/*
	2	* Configuration settings for the QUIPOS Cairo board.
	3	*
	4	* Copyright (C) DENX GmbH
	5	*
	6	* Author :
	7	* Albert ARIBAUD <albert.aribaud@3adev.fr>
	8	*
	9	* Derived from EVM code by
	10	* Manikandan Pillai <mani.pillai@ti.com>
	11	* Itself derived from Beagle Board and 3430 SDP code by
	12	* Richard Woodruff <r-woodruff2@ti.com>
	13	* Syed Mohammed Khasim <khasim@ti.com>
	14	*
	15	* Also derived from include/configs/omap3_beagle.h
	16	*
	17	* SPDX-License-Identifier: GPL-2.0+
	18	*/
	19
	20	#ifndef __OMAP3_CAIRO_CONFIG_H
	21	#define __OMAP3_CAIRO_CONFIG_H
	22
	23	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	24
	25	/*
	26	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	27	* 64 bytes before this address should be set aside for u-boot.img's
	28	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	29	* other needs. We use this rather than the inherited defines from
	30	* ti_armv7_common.h for backwards compatibility.
	31	*/
	32	#define CONFIG_SYS_TEXT_BASE 0x80100000
	33	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	34	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	35	#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
	36	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	37	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	38
	39	#define CONFIG_NAND
	40
	41	#include <configs/ti_omap3_common.h>
	42
d275c40c AA	43	#define CONFIG_MISC_INIT_R
	44
	45	#define CONFIG_REVISION_TAG 1
	46	#define CONFIG_ENV_OVERWRITE
	47
	48	/* Enable Multi Bus support for I2C */
	49	#define CONFIG_I2C_MULTI_BUS 1
	50
	51	/* Probe all devices */
	52	#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
	53
	54	#define CONFIG_NAND
	55
	56	/* commands to include */
d275c40c AA	57	#define CONFIG_CMD_NAND_LOCK_UNLOCK
d275c40c AA	58
d275c40c AA	59	/*
	60	* TWL4030
	61	*/
	62	#define CONFIG_TWL4030_LED 1
	63
	64	/*
	65	* Board NAND Info.
	66	*/
d275c40c AA	67	#define CONFIG_NAND_OMAP_GPMC
	68	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	69	/* devices */
d275c40c AA	70	#define CONFIG_EXTRA_ENV_SETTINGS \
	71	"machid=ffffffff\0" \
	72	"fdt_high=0x87000000\0" \
	73	"baudrate=115200\0" \
d275c40c AA	74	"fec_addr=00:50:C2:7E:90:F0\0" \
	75	"netmask=255.255.255.0\0" \
	76	"ipaddr=192.168.2.9\0" \
	77	"gateway=192.168.2.1\0" \
	78	"serverip=192.168.2.10\0" \
	79	"nfshost=192.168.2.10\0" \
	80	"stdin=serial\0" \
	81	"stdout=serial\0" \
	82	"stderr=serial\0" \
	83	"bootargs_mmc_ramdisk=mem=128M " \
	84	"console=ttyO1,115200n8 " \
	85	"root=/dev/ram0 rw " \
	86	"initrd=0x81600000,16M " \
	87	"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
	88	"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
	89	"mmcboot=mmc init; " \
	90	"fatload mmc 0 0x80000000 uImage; " \
	91	"fatload mmc 0 0x81600000 ramdisk.gz; " \
	92	"setenv bootargs ${bootargs_mmc_ramdisk}; " \
	93	"bootm 0x80000000\0" \
	94	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
	95	"root=/dev/nfs " \
	96	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
	97	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
	98	"omap_vout.vid1_static_vrfb_alloc=y\0" \
	99	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
	100	"bootm 0x80000000\0" \
	101	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
	102	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
	103	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
	104	"omapfb.rotate_type=1\0" \
	105	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
	106	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
	107	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	108	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	109	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
	110	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	111	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
	112	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
	113	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	114	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	115	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
	116	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
	117	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
	118	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
	119	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
	120	"nand erase 0 20000; " \
	121	"fatload mmc 0 0x81600000 MLO; " \
	122	"nandecc hw; " \
	123	"nand write.i 0x81600000 0 20000;\0" \
	124	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
	125	"nand erase 80000 40000; " \
	126	"fatload mmc 0 0x81600000 u-boot.bin; " \
	127	"nandecc sw; " \
	128	"nand write.i 0x81600000 80000 40000;\0" \
	129	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
	130	"nand erase 280000 300000; " \
	131	"fatload mmc 0 0x81600000 uImage; " \
	132	"nandecc sw; " \
	133	"nand write.i 0x81600000 280000 300000;\0" \
	134	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
	135	"nandecc sw; " \
	136	"nand write.jffs2 0x680000 0xFF ${filesize}; " \
	137	"nand erase 680000 ${filesize}; " \
138	"nand write.jffs2 81600000 680000 ${filesize};\0" \
139	"flash_scrub=nand scrub; " \
140	"run flash_xloader; " \
141	"run flash_uboot; " \
142	"run flash_kernel; " \
143	"run flash_rootfs;\0" \
144	"flash_all=run ledred; " \
145	"nand erase.chip; " \
146	"run ledorange; " \
147	"run flash_xloader; " \
148	"run flash_uboot; " \
149	"run flash_kernel; " \
150	"run flash_rootfs; " \
151	"run ledgreen; " \
152	"run boot_nand; \0" \
153
154	#define CONFIG_BOOTCOMMAND \
155	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
156	"else run boot_nand; fi"
157
158	/*
159	* OMAP3 has 12 GP timers, they can be driven by the system clock
160	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
161	* This rate is divided by a local divisor.
162	*/
163	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
164
165	/*-----------------------------------------------------------------------
166	* FLASH and environment organization
167	*/
168
169	/* ** PISMO SUPPORT * */
170	#if defined(CONFIG_CMD_NAND)
171	#define CONFIG_SYS_FLASH_BASE NAND_BASE
172	#endif
173
174	/* Monitor at start of flash */
175	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
176	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
177
178	#define CONFIG_ENV_IS_IN_NAND 1
179	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
180	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
181	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
182
183	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
184	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
185	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
186
187	#define CONFIG_OMAP3_SPI
188
d275c40c AA	189	/* Defines for SPL */
	190	#define CONFIG_SPL_OMAP3_ID_NAND
	191
	192	/* NAND boot config */
	193	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	194	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	195	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	196	#define CONFIG_SYS_NAND_OOBSIZE 64
	197	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	198	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	199	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	200	10, 11, 12, 13}
	201	#define CONFIG_SYS_NAND_ECCSIZE 512
	202	#define CONFIG_SYS_NAND_ECCBYTES 3
	203	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
	204	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	205	/* NAND: SPL falcon mode configs */
	206	#ifdef CONFIG_SPL_OS_BOOT
	207	#define CONFIG_CMD_SPL_NAND_OFS 0x240000
	208	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
	209	#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
	210	#endif
	211
	212	/* env defaults */
	213	#define CONFIG_BOOTFILE "uImage"
	214
	215	/* Override OMAP3 common serial console configuration from UART3
	216	* to UART2.
	217	*
	218	* Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
	219	* are needed and peripheral clocks for UART2 must be enabled in
	220	* function per_clocks_enable().
	221	*/
	222	#undef CONFIG_CONS_INDEX
	223	#define CONFIG_CONS_INDEX 2
	224	#ifdef CONFIG_SPL_BUILD
	225	#undef CONFIG_SYS_NS16550_COM3
	226	#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
	227	#undef CONFIG_SERIAL3
	228	#define CONFIG_SERIAL2
	229	#endif
	230
d275c40c AA	231	/* Provide MACH_TYPE for compatibility with non-DT kernels */
	232	#define MACH_TYPE_OMAP3_CAIRO 3063
	233	#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
	234
	235	/*-----------------------------------------------------------------------
	236	* FLASH and environment organization
	237	*/
	238
	239	/* ** PISMO SUPPORT * */
	240
	241	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	242	/* on one chip */
	243	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	244
	245	/*-----------------------------------------------------------------------
	246	* CFI FLASH driver setup
	247	*/
	248	/* timeout values are in ticks */
	249	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	250	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	251
	252	/* Flash banks JFFS2 should use */
	253	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	254	CONFIG_SYS_MAX_NAND_DEVICE)
	255	#define CONFIG_SYS_JFFS2_MEM_NAND
	256	/* use flash_info[2] */
	257	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	258	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	259
	260	#endif /* __OMAP3_CAIRO_CONFIG_H */