[people/ms/u-boot.git] / include / configs / omap3_evm.h

/*
 * Configuration settings for the TI OMAP3 EVM board.
 *
 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Author :
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Manikandan Pillai <mani.pillai@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __OMAP3EVM_CONFIG_H
#define __OMAP3EVM_CONFIG_H

#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>

/* ----------------------------------------------------------------------------
 * Supported U-Boot commands
 * ----------------------------------------------------------------------------
 */

#define CONFIG_CMD_JFFS2

#define CONFIG_CMD_NAND

/* ----------------------------------------------------------------------------
 * Supported U-Boot features
 * ----------------------------------------------------------------------------
 */
#define CONFIG_SYS_LONGHELP

/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Add auto-completion support */
#define CONFIG_AUTO_COMPLETE

/* ----------------------------------------------------------------------------
 * Supported hardware
 * ----------------------------------------------------------------------------
 */

/* MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC

/* SPL */
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

/* Partition tables */
#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION

/* USB
 *
 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
 * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
 */
#define CONFIG_USB_OMAP3
#define CONFIG_USB_MUSB_HCD
/* #define CONFIG_USB_MUSB_UDC */

/* NAND SPL */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * High level configuration options
 */
#define CONFIG_OMAP			/* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SDRC			/* The chip has SDRC controller */

#define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
#define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */

/*
 * Clock related definitions
 */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/* Size of environment - 128KB */
#define CONFIG_ENV_SIZE			(128 << 10)

/* Size of malloc pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Physical Memory Map
 * Note 1: CS1 may or may not be populated
 * Note 2: SDRAM size is expected to be at least 32MB
 */
#define CONFIG_NR_DRAM_BANKS		2
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* Limits for memtest */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
						0x01F00000) /* 31MB */

/* Default load address */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)

/* -----------------------------------------------------------------------------
 * Hardware drivers
 * -----------------------------------------------------------------------------
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * PISMO support
 */
/* Monitor at start of flash - Reserve 2 sectors */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/* Start location & size of environment */
#define ONENAND_ENV_OFFSET		0x260000
#define SMNAND_ENV_OFFSET		0x260000

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */

/*
 * NAND
 */
/* Physical address to access NAND */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE

/* Physical address to access NAND at CS0 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE

/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
						CONFIG_SYS_MAX_NAND_DEVICE)

#define CONFIG_SYS_JFFS2_MEM_NAND
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* Start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
/* Size of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		0xf980000

/*
 * USB
 */
#ifdef CONFIG_USB_OMAP3

#ifdef CONFIG_USB_MUSB_HCD

#define CONGIG_CMD_STORAGE

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT			"usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_USB_MUSB_HCD */

#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"EVM"
#endif /* CONFIG_USB_MUSB_UDC */

#endif /* CONFIG_USB_OMAP3 */

/* ----------------------------------------------------------------------------
 * U-Boot features
 * ----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MAXARGS		16	/* max args for a command */

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Size of Console IO buffer */
#define CONFIG_SYS_CBSIZE		512

/* Size of print buffer */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/* Size of bootarg buffer */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_BOOTFILE			"uImage"

/*
 * NAND / OneNAND
 */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
#endif

#if !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_CMD_NAND)
#define CONFIG_ENV_IS_IN_NAND
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND
#define CONFIG_ENV_OFFSET		ONENAND_ENV_OFFSET
#endif
#endif /* CONFIG_ENV_IS_NOWHERE */

#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET

#if defined(CONFIG_CMD_NET)

/* Ethernet (SMSC9115 from SMSC9118 family) */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE		0x2C000000

/* BOOTP fields */
#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010

#endif /* CONFIG_CMD_NET */

/* Support for relocation */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* -----------------------------------------------------------------------------
 * Board specific
 * -----------------------------------------------------------------------------
 */
#define CONFIG_SYS_NO_FLASH

/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

/* -----------------------------------------------------------------------------
 * Default environment
 * -----------------------------------------------------------------------------
 */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"mmcdev=0\0" \
	"console=ttyO0,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#endif /* __OMAP3EVM_CONFIG_H */
Commit	Line	Data
ad9bc8e5	1	/*
741de266 SP	2	* Configuration settings for the TI OMAP3 EVM board.
	3	*
	4	* Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
ad9bc8e5 DB	6	* Author :
	7	* Manikandan Pillai <mani.pillai@ti.com>
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
	12	* Manikandan Pillai <mani.pillai@ti.com>
	13	*
3765b3e7	14	* SPDX-License-Identifier: GPL-2.0+
ad9bc8e5 DB	15	*/
ad9bc8e5 DB	16
741de266 SP	17	#ifndef __OMAP3EVM_CONFIG_H
	18	#define __OMAP3EVM_CONFIG_H
	19
	20	#include <asm/arch/cpu.h>
987ec585	21	#include <asm/arch/omap.h>
741de266	22
741de266	23	/* ----------------------------------------------------------------------------
a187559e	24	* Supported U-Boot commands
741de266 SP	25	* ----------------------------------------------------------------------------
741de266 SP	26	*/
1ee6d31f	27
3970884c	28	#define CONFIG_CMD_JFFS2
741de266	29
3970884c	30	#define CONFIG_CMD_NAND
741de266	31
741de266	32	/* ----------------------------------------------------------------------------
a187559e	33	* Supported U-Boot features
741de266 SP	34	* ----------------------------------------------------------------------------
	35	*/
	36	#define CONFIG_SYS_LONGHELP
741de266 SP	37
	38	/* Display CPU and Board information */
	39	#define CONFIG_DISPLAY_CPUINFO
	40	#define CONFIG_DISPLAY_BOARDINFO
	41
	42	/* Allow to overwrite serial and ethaddr */
	43	#define CONFIG_ENV_OVERWRITE
	44
	45	/* Add auto-completion support */
	46	#define CONFIG_AUTO_COMPLETE
	47
	48	/* ----------------------------------------------------------------------------
	49	* Supported hardware
	50	* ----------------------------------------------------------------------------
	51	*/
	52
	53	/* MMC */
	54	#define CONFIG_MMC
	55	#define CONFIG_GENERIC_MMC
	56	#define CONFIG_OMAP_HSMMC
673283f3 TR	57
	58	/* SPL */
	59	#define CONFIG_SPL_MMC_SUPPORT
673283f3 TR	60	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
673283f3 TR	61	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
e2ccdf89	62	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	63	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
673283f3 TR	64
673283f3 TR	65	/* Partition tables */
35e3f6d7	66	#define CONFIG_EFI_PARTITION
673283f3	67	#define CONFIG_DOS_PARTITION
741de266 SP	68
	69	/* USB
	70	*
95de1e2f PK	71	* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
95de1e2f PK	72	* Enable CONFIG_USB_MUSB_UDD for Device functionalities.
741de266 SP	73	*/
741de266 SP	74	#define CONFIG_USB_OMAP3
95de1e2f PK	75	#define CONFIG_USB_MUSB_HCD
95de1e2f PK	76	/* #define CONFIG_USB_MUSB_UDC */
741de266	77
673283f3 TR	78	/* NAND SPL */
	79	#define CONFIG_SPL_NAND_SIMPLE
	80	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	81	#define CONFIG_SPL_NAND_BASE
	82	#define CONFIG_SPL_NAND_DRIVERS
	83	#define CONFIG_SPL_NAND_ECC
673283f3 TR	84	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	85	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	86	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	87	#define CONFIG_SYS_NAND_OOBSIZE 64
	88	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	89	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	90	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	91	10, 11, 12, 13}
	92	#define CONFIG_SYS_NAND_ECCSIZE 512
	93	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	94	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
673283f3 TR	95	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	96	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	97
584550d7 TR	98	/*
	99	* High level configuration options
	100	*/
	101	#define CONFIG_OMAP /* This is TI OMAP core */
	102	#define CONFIG_OMAP_GPIO
	103	#define CONFIG_OMAP_COMMON
	104	/* Common ARM Erratas */
	105	#define CONFIG_ARM_ERRATA_454179
	106	#define CONFIG_ARM_ERRATA_430973
	107	#define CONFIG_ARM_ERRATA_621766
	108
	109	#define CONFIG_SDRC /* The chip has SDRC controller */
	110
	111	#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
	112	#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
	113
	114	/*
	115	* Clock related definitions
	116	*/
	117	#define V_OSCK 26000000 /* Clock output from T2 */
	118	#define V_SCLK (V_OSCK >> 1)
	119
	120	/*
	121	* OMAP3 has 12 GP timers, they can be driven by the system clock
	122	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	123	* This rate is divided by a local divisor.
	124	*/
	125	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	126	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	127
	128	/* Size of environment - 128KB */
	129	#define CONFIG_ENV_SIZE (128 << 10)
	130
	131	/* Size of malloc pool */
	132	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	133
	134	/*
	135	* Physical Memory Map
	136	* Note 1: CS1 may or may not be populated
	137	* Note 2: SDRAM size is expected to be at least 32MB
	138	*/
	139	#define CONFIG_NR_DRAM_BANKS 2
	140	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	141	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	142
	143	/* Limits for memtest */
	144	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	145	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	146	0x01F00000) /* 31MB */
	147
	148	/* Default load address */
	149	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	150
741de266	151	/* -----------------------------------------------------------------------------
584550d7	152	* Hardware drivers
ee8e2254	153	* -----------------------------------------------------------------------------
ad9bc8e5	154	*/
584550d7 TR	155
	156	/*
	157	* NS16550 Configuration
	158	*/
	159	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	160
	161	#define CONFIG_SYS_NS16550_SERIAL
	162	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	163	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	164
	165	/*
	166	* select serial console configuration
	167	*/
	168	#define CONFIG_CONS_INDEX 1
	169	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
	170	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	171	#define CONFIG_BAUDRATE 115200
	172	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	173	115200}
	174
	175	/*
	176	* I2C
	177	*/
	178	#define CONFIG_SYS_I2C
	179	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	180	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	181	#define CONFIG_SYS_I2C_OMAP34XX
	182
	183	/*
	184	* PISMO support
	185	*/
	186	/* Monitor at start of flash - Reserve 2 sectors */
	187	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	188
	189	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	190
	191	/* Start location & size of environment */
	192	#define ONENAND_ENV_OFFSET 0x260000
	193	#define SMNAND_ENV_OFFSET 0x260000
	194
	195	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	196
	197	/*
	198	* NAND
	199	*/
	200	/* Physical address to access NAND */
	201	#define CONFIG_SYS_NAND_ADDR NAND_BASE
	202
	203	/* Physical address to access NAND at CS0 */
	204	#define CONFIG_SYS_NAND_BASE NAND_BASE
	205
	206	/* Max number of NAND devices */
	207	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	208	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
	209	/* Timeout values (in ticks) */
	210	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	211	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	212
	213	/* Flash banks JFFS2 should use */
	214	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	215	CONFIG_SYS_MAX_NAND_DEVICE)
	216
	217	#define CONFIG_SYS_JFFS2_MEM_NAND
	218	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
219	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
220
221	#define CONFIG_JFFS2_NAND
222	/* nand device jffs2 lives on */
223	#define CONFIG_JFFS2_DEV "nand0"
224	/* Start of jffs2 partition */
225	#define CONFIG_JFFS2_PART_OFFSET 0x680000
226	/* Size of jffs2 partition */
227	#define CONFIG_JFFS2_PART_SIZE 0xf980000
228
229	/*
230	* USB
231	*/
232	#ifdef CONFIG_USB_OMAP3
233
234	#ifdef CONFIG_USB_MUSB_HCD
235
584550d7 TR	236	#define CONGIG_CMD_STORAGE
	237
	238	#ifdef CONFIG_USB_KEYBOARD
	239	#define CONFIG_SYS_USB_EVENT_POLL
	240	#define CONFIG_PREBOOT "usb start"
	241	#endif /* CONFIG_USB_KEYBOARD */
	242
	243	#endif /* CONFIG_USB_MUSB_HCD */
	244
	245	#ifdef CONFIG_USB_MUSB_UDC
	246	/* USB device configuration */
	247	#define CONFIG_USB_DEVICE
	248	#define CONFIG_USB_TTY
	249	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	250
	251	/* Change these to suit your needs */
	252	#define CONFIG_USBD_VENDORID 0x0451
	253	#define CONFIG_USBD_PRODUCTID 0x5678
	254	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	255	#define CONFIG_USBD_PRODUCT_NAME "EVM"
	256	#endif /* CONFIG_USB_MUSB_UDC */
	257
	258	#endif /* CONFIG_USB_OMAP3 */
	259
	260	/* ----------------------------------------------------------------------------
	261	* U-Boot features
	262	* ----------------------------------------------------------------------------
	263	*/
	264	#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
	265
	266	#define CONFIG_MISC_INIT_R
	267
	268	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	269	#define CONFIG_SETUP_MEMORY_TAGS
	270	#define CONFIG_INITRD_TAG
	271	#define CONFIG_REVISION_TAG
	272
	273	/* Size of Console IO buffer */
	274	#define CONFIG_SYS_CBSIZE 512
	275
	276	/* Size of print buffer */
	277	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	278	sizeof(CONFIG_SYS_PROMPT) + 16)
	279
	280	/* Size of bootarg buffer */
	281	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	282
	283	#define CONFIG_BOOTFILE "uImage"
	284
	285	/*
	286	* NAND / OneNAND
	287	*/
	288	#if defined(CONFIG_CMD_NAND)
	289	#define CONFIG_SYS_FLASH_BASE NAND_BASE
	290
	291	#define CONFIG_NAND_OMAP_GPMC
	292	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	293	#elif defined(CONFIG_CMD_ONENAND)
	294	#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
	295	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	296	#endif
	297
	298	#if !defined(CONFIG_ENV_IS_NOWHERE)
	299	#if defined(CONFIG_CMD_NAND)
300	#define CONFIG_ENV_IS_IN_NAND
301	#elif defined(CONFIG_CMD_ONENAND)
302	#define CONFIG_ENV_IS_IN_ONENAND
303	#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
304	#endif
305	#endif /* CONFIG_ENV_IS_NOWHERE */
306
307	#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
308
309	#if defined(CONFIG_CMD_NET)
310
311	/* Ethernet (SMSC9115 from SMSC9118 family) */
312	#define CONFIG_SMC911X
313	#define CONFIG_SMC911X_32_BIT
314	#define CONFIG_SMC911X_BASE 0x2C000000
315
316	/* BOOTP fields */
317	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
318	#define CONFIG_BOOTP_GATEWAY 0x00000002
319	#define CONFIG_BOOTP_HOSTNAME 0x00000004
320	#define CONFIG_BOOTP_BOOTPATH 0x00000010
321
322	#endif /* CONFIG_CMD_NET */
323
324	/* Support for relocation */
325	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
326	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
327	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
328	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
329	CONFIG_SYS_INIT_RAM_SIZE - \
330	GENERATED_GBL_DATA_SIZE)
331
332	/* -----------------------------------------------------------------------------
333	* Board specific
334	* -----------------------------------------------------------------------------
335	*/
336	#define CONFIG_SYS_NO_FLASH
337
338	/* Uncomment to define the board revision statically */
339	/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
340
584550d7 TR	341	/* Defines for SPL */
	342	#define CONFIG_SPL_FRAMEWORK
	343	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	344	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	345	CONFIG_SPL_TEXT_BASE)
584550d7 TR	346
	347	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	348	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	349
	350	#define CONFIG_SPL_BOARD_INIT
584550d7 TR	351	#define CONFIG_SPL_SERIAL_SUPPORT
	352	#define CONFIG_SPL_POWER_SUPPORT
	353	#define CONFIG_SPL_OMAP3_ID_NAND
	354	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	355
	356	/*
	357	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	358	* 64 bytes before this address should be set aside for u-boot.img's
	359	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	360	* other needs.
	361	*/
	362	#define CONFIG_SYS_TEXT_BASE 0x80100000
	363	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	364	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
ad9bc8e5	365
ee8e2254 SP	366	/* -----------------------------------------------------------------------------
	367	* Default environment
	368	* -----------------------------------------------------------------------------
	369	*/
136cf92d	370
ad9bc8e5 DB	371	#define CONFIG_EXTRA_ENV_SETTINGS \
ad9bc8e5 DB	372	"loadaddr=0x82000000\0" \
73c8640e	373	"usbtty=cdc_acm\0" \
dcc4f38b	374	"mmcdev=0\0" \
effeda55	375	"console=ttyO0,115200n8\0" \
ad9bc8e5 DB	376	"mmcargs=setenv bootargs console=${console} " \
	377	"root=/dev/mmcblk0p2 rw " \
	378	"rootfstype=ext3 rootwait\0" \
	379	"nandargs=setenv bootargs console=${console} " \
	380	"root=/dev/mtdblock4 rw " \
	381	"rootfstype=jffs2\0" \
dcc4f38b	382	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
ad9bc8e5	383	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	384	"source ${loadaddr}\0" \
dcc4f38b	385	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
ad9bc8e5 DB	386	"mmcboot=echo Booting from mmc ...; " \
	387	"run mmcargs; " \
	388	"bootm ${loadaddr}\0" \
	389	"nandboot=echo Booting from nand ...; " \
	390	"run nandargs; " \
	391	"onenand read ${loadaddr} 280000 400000; " \
	392	"bootm ${loadaddr}\0" \
	393
	394	#define CONFIG_BOOTCOMMAND \
66968110	395	"mmc dev ${mmcdev}; if mmc rescan; then " \
ad9bc8e5 DB	396	"if run loadbootscript; then " \
	397	"run bootscript; " \
	398	"else " \
	399	"if run loaduimage; then " \
	400	"run mmcboot; " \
	401	"else run nandboot; " \
	402	"fi; " \
	403	"fi; " \
	404	"else run nandboot; fi"
	405
741de266	406	#endif /* __OMAP3EVM_CONFIG_H */