[people/ms/u-boot.git] / include / configs / omap3_evm_common.h

/*
 * Common configuration settings for the TI OMAP3 EVM board.
 *
 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __OMAP3_EVM_COMMON_H
#define __OMAP3_EVM_COMMON_H

/*
 * High level configuration options
 */
#define CONFIG_OMAP			/* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SDRC			/* The chip has SDRC controller */

#define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
#define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */

/*
 * Clock related definitions
 */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/* Size of environment - 128KB */
#define CONFIG_ENV_SIZE			(128 << 10)

/* Size of malloc pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Physical Memory Map
 * Note 1: CS1 may or may not be populated
 * Note 2: SDRAM size is expected to be at least 32MB
 */
#define CONFIG_NR_DRAM_BANKS		2
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* Limits for memtest */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
						0x01F00000) /* 31MB */

/* Default load address */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)

/* -----------------------------------------------------------------------------
 * Hardware drivers
 * -----------------------------------------------------------------------------
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * PISMO support
 */
/* Monitor at start of flash - Reserve 2 sectors */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/* Start location & size of environment */
#define ONENAND_ENV_OFFSET		0x260000
#define SMNAND_ENV_OFFSET		0x260000

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */

/*
 * NAND
 */
/* Physical address to access NAND */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE

/* Physical address to access NAND at CS0 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE

/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
						CONFIG_SYS_MAX_NAND_DEVICE)

#define CONFIG_SYS_JFFS2_MEM_NAND
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* Start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
/* Size of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		0xf980000

/*
 * USB
 */
#ifdef CONFIG_USB_OMAP3

#ifdef CONFIG_USB_MUSB_HCD
#define CONFIG_CMD_USB

#define CONFIG_USB_STORAGE
#define CONGIG_CMD_STORAGE
#define CONFIG_CMD_FAT

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT			"usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_USB_MUSB_HCD */

#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"EVM"
#endif /* CONFIG_USB_MUSB_UDC */

#endif /* CONFIG_USB_OMAP3 */

/* ----------------------------------------------------------------------------
 * U-boot features
 * ----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MAXARGS		16	/* max args for a command */

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Size of Console IO buffer */
#define CONFIG_SYS_CBSIZE		512

/* Size of print buffer */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/* Size of bootarg buffer */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_BOOTFILE			"uImage"

/*
 * NAND / OneNAND
 */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
#endif

#if !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_CMD_NAND)
#define CONFIG_ENV_IS_IN_NAND
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND
#define CONFIG_ENV_OFFSET		ONENAND_ENV_OFFSET
#endif
#endif /* CONFIG_ENV_IS_NOWHERE */

#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET

#if defined(CONFIG_CMD_NET)

/* Ethernet (SMSC9115 from SMSC9118 family) */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE		0x2C000000

/* BOOTP fields */
#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010

#endif /* CONFIG_CMD_NET */

/* Support for relocation */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* -----------------------------------------------------------------------------
 * Board specific
 * -----------------------------------------------------------------------------
 */
#define CONFIG_SYS_NO_FLASH

/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */

#define CONFIG_SYS_CACHELINE_SIZE	64

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __OMAP3_EVM_COMMON_H */
Commit	Line	Data
3970884c SP	1	/*
	2	* Common configuration settings for the TI OMAP3 EVM board.
	3	*
	4	* Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
3970884c SP	7	*/
	8
	9	#ifndef __OMAP3_EVM_COMMON_H
	10	#define __OMAP3_EVM_COMMON_H
	11
	12	/*
	13	* High level configuration options
	14	*/
	15	#define CONFIG_OMAP /* This is TI OMAP core */
308252ad	16	#define CONFIG_OMAP_GPIO
806d2792	17	#define CONFIG_OMAP_COMMON
c6f90e14 NM	18	/* Common ARM Erratas */
	19	#define CONFIG_ARM_ERRATA_454179
	20	#define CONFIG_ARM_ERRATA_430973
	21	#define CONFIG_ARM_ERRATA_621766
3970884c SP	22
	23	#define CONFIG_SDRC /* The chip has SDRC controller */
	24
	25	#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
3970884c SP	26	#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
3970884c SP	27
3970884c SP	28	/*
	29	* Clock related definitions
	30	*/
	31	#define V_OSCK 26000000 /* Clock output from T2 */
	32	#define V_SCLK (V_OSCK >> 1)
	33
	34	/*
	35	* OMAP3 has 12 GP timers, they can be driven by the system clock
	36	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	37	* This rate is divided by a local divisor.
	38	*/
	39	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	40	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
3970884c SP	41
	42	/* Size of environment - 128KB */
	43	#define CONFIG_ENV_SIZE (128 << 10)
	44
	45	/* Size of malloc pool */
	46	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	47
3970884c SP	48	/*
	49	* Physical Memory Map
	50	* Note 1: CS1 may or may not be populated
	51	* Note 2: SDRAM size is expected to be at least 32MB
	52	*/
	53	#define CONFIG_NR_DRAM_BANKS 2
	54	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
3970884c SP	55	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
3970884c SP	56
3970884c SP	57	/* Limits for memtest */
	58	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	59	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	60	0x01F00000) /* 31MB */
	61
	62	/* Default load address */
	63	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	64
	65	/* -----------------------------------------------------------------------------
	66	* Hardware drivers
	67	* -----------------------------------------------------------------------------
	68	*/
	69
	70	/*
	71	* NS16550 Configuration
	72	*/
	73	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	74
3970884c SP	75	#define CONFIG_SYS_NS16550_SERIAL
	76	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	77	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	78
	79	/*
	80	* select serial console configuration
	81	*/
	82	#define CONFIG_CONS_INDEX 1
	83	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
	84	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	85	#define CONFIG_BAUDRATE 115200
	86	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	87	115200}
	88
	89	/*
	90	* I2C
	91	*/
6789e84e HS	92	#define CONFIG_SYS_I2C
	93	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	94	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	95	#define CONFIG_SYS_I2C_OMAP34XX
3970884c SP	96
	97	/*
	98	* PISMO support
	99	*/
3970884c SP	100	/* Monitor at start of flash - Reserve 2 sectors */
	101	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	102
	103	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	104
	105	/* Start location & size of environment */
	106	#define ONENAND_ENV_OFFSET 0x260000
	107	#define SMNAND_ENV_OFFSET 0x260000
	108
	109	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	110
	111	/*
	112	* NAND
	113	*/
	114	/* Physical address to access NAND */
	115	#define CONFIG_SYS_NAND_ADDR NAND_BASE
	116
	117	/* Physical address to access NAND at CS0 */
	118	#define CONFIG_SYS_NAND_BASE NAND_BASE
	119
	120	/* Max number of NAND devices */
	121	#define CONFIG_SYS_MAX_NAND_DEVICE 1
55f1b39f	122	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
3970884c SP	123	/* Timeout values (in ticks) */
	124	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	125	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	126
	127	/* Flash banks JFFS2 should use */
	128	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	129	CONFIG_SYS_MAX_NAND_DEVICE)
	130
	131	#define CONFIG_SYS_JFFS2_MEM_NAND
	132	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	133	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	134
	135	#define CONFIG_JFFS2_NAND
	136	/* nand device jffs2 lives on */
	137	#define CONFIG_JFFS2_DEV "nand0"
	138	/* Start of jffs2 partition */
	139	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	140	/* Size of jffs2 partition */
	141	#define CONFIG_JFFS2_PART_SIZE 0xf980000
	142
	143	/*
	144	* USB
	145	*/
	146	#ifdef CONFIG_USB_OMAP3
	147
95de1e2f	148	#ifdef CONFIG_USB_MUSB_HCD
3970884c SP	149	#define CONFIG_CMD_USB
	150
	151	#define CONFIG_USB_STORAGE
	152	#define CONGIG_CMD_STORAGE
	153	#define CONFIG_CMD_FAT
	154
	155	#ifdef CONFIG_USB_KEYBOARD
	156	#define CONFIG_SYS_USB_EVENT_POLL
	157	#define CONFIG_PREBOOT "usb start"
	158	#endif /* CONFIG_USB_KEYBOARD */
	159
95de1e2f	160	#endif /* CONFIG_USB_MUSB_HCD */
3970884c	161
95de1e2f	162	#ifdef CONFIG_USB_MUSB_UDC
3970884c SP	163	/* USB device configuration */
	164	#define CONFIG_USB_DEVICE
	165	#define CONFIG_USB_TTY
	166	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	167
	168	/* Change these to suit your needs */
	169	#define CONFIG_USBD_VENDORID 0x0451
	170	#define CONFIG_USBD_PRODUCTID 0x5678
	171	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	172	#define CONFIG_USBD_PRODUCT_NAME "EVM"
95de1e2f	173	#endif /* CONFIG_USB_MUSB_UDC */
3970884c SP	174
	175	#endif /* CONFIG_USB_OMAP3 */
	176
	177	/* ----------------------------------------------------------------------------
	178	* U-boot features
	179	* ----------------------------------------------------------------------------
	180	*/
3970884c SP	181	#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
	182
	183	#define CONFIG_MISC_INIT_R
	184
	185	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	186	#define CONFIG_SETUP_MEMORY_TAGS
	187	#define CONFIG_INITRD_TAG
	188	#define CONFIG_REVISION_TAG
	189
	190	/* Size of Console IO buffer */
	191	#define CONFIG_SYS_CBSIZE 512
	192
	193	/* Size of print buffer */
	194	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	195	sizeof(CONFIG_SYS_PROMPT) + 16)
	196
	197	/* Size of bootarg buffer */
	198	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	199
	200	#define CONFIG_BOOTFILE "uImage"
	201
	202	/*
	203	* NAND / OneNAND
	204	*/
	205	#if defined(CONFIG_CMD_NAND)
222a3113	206	#define CONFIG_SYS_FLASH_BASE NAND_BASE
3970884c SP	207
3970884c SP	208	#define CONFIG_NAND_OMAP_GPMC
3970884c SP	209	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
3970884c SP	210	#elif defined(CONFIG_CMD_ONENAND)
222a3113	211	#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
3970884c	212	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
edc633ea	213	#endif
3970884c	214
edc633ea SP	215	#if !defined(CONFIG_ENV_IS_NOWHERE)
	216	#if defined(CONFIG_CMD_NAND)
	217	#define CONFIG_ENV_IS_IN_NAND
	218	#elif defined(CONFIG_CMD_ONENAND)
3970884c SP	219	#define CONFIG_ENV_IS_IN_ONENAND
	220	#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
	221	#endif
edc633ea	222	#endif /* CONFIG_ENV_IS_NOWHERE */
3970884c SP	223
	224	#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
	225
	226	#if defined(CONFIG_CMD_NET)
	227
	228	/* Ethernet (SMSC9115 from SMSC9118 family) */
3970884c SP	229	#define CONFIG_SMC911X
	230	#define CONFIG_SMC911X_32_BIT
	231	#define CONFIG_SMC911X_BASE 0x2C000000
	232
	233	/* BOOTP fields */
	234	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	235	#define CONFIG_BOOTP_GATEWAY 0x00000002
	236	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	237	#define CONFIG_BOOTP_BOOTPATH 0x00000010
	238
	239	#endif /* CONFIG_CMD_NET */
	240
	241	/* Support for relocation */
	242	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	243	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	244	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	245	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	246	CONFIG_SYS_INIT_RAM_SIZE - \
	247	GENERATED_GBL_DATA_SIZE)
	248
	249	/* -----------------------------------------------------------------------------
	250	* Board specific
	251	* -----------------------------------------------------------------------------
	252	*/
	253	#define CONFIG_SYS_NO_FLASH
	254
	255	/* Uncomment to define the board revision statically */
	256	/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
	257
8e40852f A	258	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	259
673283f3	260	/* Defines for SPL */
47f7bcae	261	#define CONFIG_SPL_FRAMEWORK
673283f3	262	#define CONFIG_SPL_TEXT_BASE 0x40200800
e0820ccc	263	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
673283f3 TR	264
	265	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	266	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	267
49175c49	268	#define CONFIG_SPL_BOARD_INIT
673283f3 TR	269	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	270	#define CONFIG_SPL_LIBDISK_SUPPORT
	271	#define CONFIG_SPL_I2C_SUPPORT
	272	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	273	#define CONFIG_SPL_SERIAL_SUPPORT
	274	#define CONFIG_SPL_POWER_SUPPORT
	275	#define CONFIG_SPL_OMAP3_ID_NAND
	276	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	277
	278	/*
	279	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	280	* 64 bytes before this address should be set aside for u-boot.img's
	281	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	282	* other needs.
	283	*/
	284	#define CONFIG_SYS_TEXT_BASE 0x80100000
	285	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	286	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	287
3970884c	288	#endif /* __OMAP3_EVM_COMMON_H */