[people/ms/u-boot.git] / include / configs / omap3_logic.h

/*
 * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
 *	Peter Barada <peter.barada@logicpd.com>
 *
 * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
 * reference boards.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */

#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.  We use this rather than the inherited defines from
 * ti_armv7_common.h for backwards compatibility.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#include <configs/ti_omap3_common.h>

/*
 * We are only ever GP parts and will utilize all of the "downloaded image"
 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
 * order to allow for BCH8 to fit in.
 */
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE		0x40200000

#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R		/* misc_init_r dumps the die id */
#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING		/* cmd line edit/history */

/* Hardware drivers */

/* GPIO banks */
#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */

#define CONFIG_USB_OMAP3

/* select serial console configuration */
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP Logic boards */

/* commands to include */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/

/* I2C */
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM AT24C64      */
#define EXPANSION_EEPROM_I2C_BUS	2	/* I2C Bus for AT24C64 */
#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID

/* USB */
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE	0x07000000

/* TWL4030 */
#define CONFIG_TWL4030_PWM
#define CONFIG_TWL4030_USB

/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC

#define CONFIG_CMD_UBIFS		/* Read-only UBI volume operations */
#define CONFIG_RBTREE			/* required by CONFIG_CMD_UBI */
#define CONFIG_LZO			/* required by CONFIG_CMD_UBIFS */

#define CONFIG_SYS_NAND_ADDR		NAND_BASE /* physical address */
						  /* to access nand */
#define CONFIG_SYS_MAX_NAND_DEVICE	1	  /* Max number of */
						  /* NAND devices */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
					 52, 53, 54, 55, 56}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	13
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_BCH
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_MAX_ECCPOS	56
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(MLO),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"
#endif

/* Environment information */

/*
 * PREBOOT assumes the 4.3" display is attached.  User can interrupt
 * and modify display variable to suit their needs.
 */
#define CONFIG_PREBOOT \
	"echo ======================NOTICE============================;"\
	"echo \"The u-boot environment is not set.\";"			\
	"echo \"If using a display a valid display variable for your panel\";" \
	"echo \"needs to be set.\";"					\
	"echo \"Valid display options are:\";"				\
	"echo \"  2 == LQ121S1DG31     TFT SVGA    (12.1)  Sharp\";"	\
	"echo \"  3 == LQ036Q1DA01     TFT QVGA    (3.6)   Sharp w/ASIC\";" \
	"echo \"  5 == LQ064D343       TFT VGA     (6.4)   Sharp\";"	\
	"echo \"  7 == LQ10D368        TFT VGA     (10.4)  Sharp\";"	\
	"echo \" 15 == LQ043T1DG01     TFT WQVGA   (4.3)   Sharp (DEFAULT)\";" \
	"echo \" vga[-dvi or -hdmi]    LCD VGA     640x480\";"          \
	"echo \" svga[-dvi or -hdmi]   LCD SVGA    800x600\";"          \
	"echo \" xga[-dvi or -hdmi]    LCD XGA     1024x768\";"         \
	"echo \" 720p[-dvi or -hdmi]   LCD 720P    1280x720\";"         \
	"echo \"Defaulting to 4.3 LCD panel (display=15).\";"		\
	"setenv display 15;"						\
	"setenv preboot;"						\
	"nand unlock;"							\
	"saveenv;"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x81000000\0" \
	"uimage=uImage\0" \
	"zimage=zImage\0" \
	"mtdids=" MTDIDS_DEFAULT "\0"	\
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait\0" \
	"nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
	"nandrootfstype=ubifs rootwait\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"run defaultboot;" \
			"fi; " \
		"else run defaultboot; fi\0" \
	"defaultboot=run mmcramboot\0" \
	"consoledevice=ttyO0\0" \
	"display=15\0" \
	"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
	"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
	"rotation=0\0" \
	"vrfb_arg=if itest ${rotation} -ne 0; then " \
		"setenv bootargs ${bootargs} omapfb.vrfb=y " \
		"omapfb.rotate=${rotation}; " \
		"fi\0" \
	"optargs=ignore_loglevel early_printk no_console_suspend\0" \
	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
	"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
		"${optargs};" \
		"run addmtdparts; " \
		"run vrfb_arg\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo 'Running bootscript from mmc ...'; " \
		"source ${loadaddr}\0" \
	"loaduimage=mmc rescan; " \
		"fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
	"loadzimage=mmc rescan; " \
		"fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
	"ramdisksize=64000\0" \
	"ramdiskaddr=0x82000000\0" \
	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
	"loadramdisk=mmc rescan; " \
		"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
	"ramargs=run setconsole; setenv bootargs console=${console} " \
		"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
	"mmcargs=run setconsole; setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=run setconsole; setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"fdtaddr=0x86000000\0" \
	"loadfdtimage=mmc rescan; " \
		"fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
		"run mmcargs; " \
		"run common_bootargs; " \
		"run dump_bootargs; " \
		"run loadzimage; " \
		"run loadfdtimage; " \
		"bootz ${loadaddr} - ${fdtaddr}\0" \
	"mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
		"run ramargs; " \
		"run common_bootargs; " \
		"run dump_bootargs; " \
		"run loaduimage; " \
		"run loadramdisk; " \
		"bootm ${loadaddr} ${ramdiskaddr}\0" \
	"mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
		"run ramargs; " \
		"run common_bootargs; " \
		"run dump_bootargs; " \
		"run loadzimage; " \
		"run loadramdisk; " \
		"run loadfdtimage; " \
		"bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
	"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
		"run ramargs; " \
		"run common_bootargs; " \
		"run dump_bootargs; " \
		"tftpboot ${loadaddr} ${uimage}; " \
		"tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
		"bootm ${loadaddr} ${ramdiskaddr}\0"

#define CONFIG_BOOTCOMMAND \
	"run autoboot"

/* Miscellaneous configurable options */
#define CONFIG_AUTO_COMPLETE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

/* FLASH and environment organization */

/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/* SMSC922x Ethernet */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	0x08000000
#endif /* (CONFIG_CMD_NET) */

/* Defines for SPL */

#define CONFIG_SPL_OMAP3_ID_NAND

/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS		0x240000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
86887f8e PB	1	/*
	2	* (C) Copyright 2011 Logic Product Development <www.logicpd.com>
	3	* Peter Barada <peter.barada@logicpd.com>
	4	*
	5	* Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
	6	* reference boards.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
86887f8e PB	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
49c7303f	14	/* High Level Configuration Options */
86887f8e	15
7b77b1f6	16	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
86887f8e	17
86887f8e	18	/*
49c7303f AF	19	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	20	* 64 bytes before this address should be set aside for u-boot.img's
	21	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	22	* other needs. We use this rather than the inherited defines from
	23	* ti_armv7_common.h for backwards compatibility.
86887f8e	24	*/
49c7303f AF	25	#define CONFIG_SYS_TEXT_BASE 0x80100000
	26	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	27	#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
	28	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	29	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	30
	31	#include <configs/ti_omap3_common.h>
	32
fa2f81b0 TR	33	/*
	34	* We are only ever GP parts and will utilize all of the "downloaded image"
	35	* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
	36	* order to allow for BCH8 to fit in.
	37	*/
f92dfc87	38	#undef CONFIG_SPL_TEXT_BASE
fa2f81b0	39	#define CONFIG_SPL_TEXT_BASE 0x40200000
f92dfc87	40
26ef7a27	41	#define CONFIG_BOARD_LATE_INIT
86887f8e	42	#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
49c7303f	43	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
86887f8e PB	44	#define CONFIG_SETUP_MEMORY_TAGS
	45	#define CONFIG_INITRD_TAG
	46	#define CONFIG_REVISION_TAG
49c7303f	47	#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
86887f8e	48
49c7303f	49	/* Hardware drivers */
86887f8e	50
b99353b8 AF	51	/* GPIO banks */
	52	#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
	53
49c7303f AF	54	#define CONFIG_USB_OMAP3
	55
	56	/* select serial console configuration */
7b77b1f6	57	#undef CONFIG_CONS_INDEX
86887f8e PB	58	#define CONFIG_CONS_INDEX 1
	59	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	60	#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
	61
86887f8e	62	/* commands to include */
49c7303f	63	#define CONFIG_CMD_NAND
49c7303f	64	#define CONFIG_CMD_MTDPARTS
86887f8e	65	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
86887f8e	66
49c7303f	67	/* I2C */
6789e84e	68	#define CONFIG_SYS_I2C_OMAP34XX
49c7303f AF	69	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
	70	#define EXPANSION_EEPROM_I2C_BUS 2 /* I2C Bus for AT24C64 */
	71	#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
86887f8e	72
588e41d2	73	/* USB */
588e41d2 AF	74	#define CONFIG_USB_MUSB_OMAP2PLUS
588e41d2 AF	75	#define CONFIG_USB_MUSB_PIO_ONLY
588e41d2 AF	76	#define CONFIG_USB_ETHER
588e41d2 AF	77	#define CONFIG_USB_ETHER_RNDIS
588e41d2 AF	78	#define CONFIG_USB_FUNCTION_FASTBOOT
	79	#define CONFIG_CMD_FASTBOOT
	80	#define CONFIG_ANDROID_BOOT_IMAGE
	81	#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
	82	#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
588e41d2	83
49c7303f AF	84	/* TWL4030 */
49c7303f AF	85	#define CONFIG_TWL4030_PWM
588e41d2	86	#define CONFIG_TWL4030_USB
7b77b1f6	87
49c7303f AF	88	/* Board NAND Info. */
49c7303f AF	89	#ifdef CONFIG_NAND
86887f8e	90	#define CONFIG_NAND_OMAP_GPMC
7b77b1f6	91
49c7303f AF	92	#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
	93	#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
	94	#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
86887f8e	95
49c7303f AF	96	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	97	/* to access nand */
	98	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	99	/* NAND devices */
55f1b39f	100	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
49c7303f AF	101	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	102	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	103	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	104	#define CONFIG_SYS_NAND_OOBSIZE 64
	105	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	106	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	107	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
	108	13, 14, 16, 17, 18, 19, 20, 21, 22, \
	109	23, 24, 25, 26, 27, 28, 30, 31, 32, \
	110	33, 34, 35, 36, 37, 38, 39, 40, 41, \
	111	42, 44, 45, 46, 47, 48, 49, 50, 51, \
	112	52, 53, 54, 55, 56}
	113
	114	#define CONFIG_SYS_NAND_ECCSIZE 512
	115	#define CONFIG_SYS_NAND_ECCBYTES 13
	116	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	117	#define CONFIG_BCH
	118	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	119	#define CONFIG_SYS_NAND_MAX_ECCPOS 56
	120	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	121	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	122	#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
	123	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	124	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\
	125	"1920k(u-boot),128k(u-boot-env),"\
	126	"4m(kernel),-(fs)"
	127	#endif
86887f8e PB	128
86887f8e PB	129	/* Environment information */
86887f8e PB	130
	131	/*
	132	* PREBOOT assumes the 4.3" display is attached. User can interrupt
	133	* and modify display variable to suit their needs.
	134	*/
	135	#define CONFIG_PREBOOT \
	136	"echo ======================NOTICE============================;"\
	137	"echo \"The u-boot environment is not set.\";" \
1cc0a9f4	138	"echo \"If using a display a valid display variable for your panel\";" \
86887f8e PB	139	"echo \"needs to be set.\";" \
	140	"echo \"Valid display options are:\";" \
	141	"echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
	142	"echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
	143	"echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
	144	"echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
	145	"echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
	146	"echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
	147	"echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
	148	"echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
	149	"echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
	150	"echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
	151	"setenv display 15;" \
	152	"setenv preboot;" \
49c7303f	153	"nand unlock;" \
86887f8e PB	154	"saveenv;"
86887f8e PB	155
86887f8e PB	156	#define CONFIG_EXTRA_ENV_SETTINGS \
86887f8e PB	157	"loadaddr=0x81000000\0" \
49c7303f AF	158	"uimage=uImage\0" \
49c7303f AF	159	"zimage=zImage\0" \
86887f8e PB	160	"mtdids=" MTDIDS_DEFAULT "\0" \
	161	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	162	"mmcdev=0\0" \
49c7303f AF	163	"mmcroot=/dev/mmcblk0p2 rw\0" \
49c7303f AF	164	"mmcrootfstype=ext4 rootwait\0" \
a094c921 AF	165	"nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
a094c921 AF	166	"nandrootfstype=ubifs rootwait\0" \
66968110	167	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
86887f8e PB	168	"if run loadbootscript; then " \
	169	"run bootscript; " \
	170	"else " \
	171	"run defaultboot;" \
	172	"fi; " \
	173	"else run defaultboot; fi\0" \
	174	"defaultboot=run mmcramboot\0" \
	175	"consoledevice=ttyO0\0" \
	176	"display=15\0" \
	177	"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
	178	"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
	179	"rotation=0\0" \
	180	"vrfb_arg=if itest ${rotation} -ne 0; then " \
	181	"setenv bootargs ${bootargs} omapfb.vrfb=y " \
	182	"omapfb.rotate=${rotation}; " \
	183	"fi\0" \
49c7303f	184	"optargs=ignore_loglevel early_printk no_console_suspend\0" \
86887f8e PB	185	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
86887f8e PB	186	"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
49c7303f	187	"${optargs};" \
86887f8e PB	188	"run addmtdparts; " \
	189	"run vrfb_arg\0" \
	190	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	191	"bootscript=echo 'Running bootscript from mmc ...'; " \
	192	"source ${loadaddr}\0" \
49c7303f AF	193	"loaduimage=mmc rescan; " \
	194	"fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
	195	"loadzimage=mmc rescan; " \
	196	"fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
86887f8e PB	197	"ramdisksize=64000\0" \
	198	"ramdiskaddr=0x82000000\0" \
	199	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
49c7303f AF	200	"loadramdisk=mmc rescan; " \
49c7303f AF	201	"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
86887f8e PB	202	"ramargs=run setconsole; setenv bootargs console=${console} " \
86887f8e PB	203	"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
49c7303f AF	204	"mmcargs=run setconsole; setenv bootargs console=${console} " \
	205	"${optargs} " \
	206	"root=${mmcroot} " \
	207	"rootfstype=${mmcrootfstype}\0" \
a094c921 AF	208	"nandargs=run setconsole; setenv bootargs console=${console} " \
	209	"${optargs} " \
	210	"root=${nandroot} " \
	211	"rootfstype=${nandrootfstype}\0" \
49c7303f AF	212	"fdtaddr=0x86000000\0" \
	213	"loadfdtimage=mmc rescan; " \
	214	"fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
	215	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
	216	"run mmcargs; " \
	217	"run common_bootargs; " \
	218	"run dump_bootargs; " \
	219	"run loadzimage; " \
	220	"run loadfdtimage; " \
	221	"bootz ${loadaddr} - ${fdtaddr}\0" \
	222	"mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
86887f8e PB	223	"run ramargs; " \
	224	"run common_bootargs; " \
	225	"run dump_bootargs; " \
	226	"run loaduimage; " \
49c7303f	227	"run loadramdisk; " \
86887f8e	228	"bootm ${loadaddr} ${ramdiskaddr}\0" \
49c7303f	229	"mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
86887f8e PB	230	"run ramargs; " \
	231	"run common_bootargs; " \
	232	"run dump_bootargs; " \
49c7303f AF	233	"run loadzimage; " \
	234	"run loadramdisk; " \
	235	"run loadfdtimage; " \
	236	"bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
	237	"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
	238	"run ramargs; " \
	239	"run common_bootargs; " \
	240	"run dump_bootargs; " \
	241	"tftpboot ${loadaddr} ${uimage}; " \
	242	"tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
86887f8e PB	243	"bootm ${loadaddr} ${ramdiskaddr}\0"
	244
	245	#define CONFIG_BOOTCOMMAND \
	246	"run autoboot"
	247
49c7303f	248	/* Miscellaneous configurable options */
86887f8e	249	#define CONFIG_AUTO_COMPLETE
7b77b1f6	250
86887f8e PB	251	/* memtest works on */
	252	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	253	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	254	0x01F00000) /* 31MB */
	255
49c7303f	256	/* FLASH and environment organization */
86887f8e PB	257
86887f8e PB	258	/* ** PISMO SUPPORT * */
86887f8e	259	#if defined(CONFIG_CMD_NAND)
222a3113	260	#define CONFIG_SYS_FLASH_BASE NAND_BASE
86887f8e	261	#elif defined(CONFIG_CMD_ONENAND)
222a3113	262	#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
86887f8e PB	263	#endif
	264
	265	/* Monitor at start of flash */
	266	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	267
49c7303f AF	268	#define CONFIG_ENV_IS_IN_NAND 1
	269	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
	270	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
86887f8e PB	271	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
86887f8e PB	272
86887f8e	273	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
49c7303f AF	274	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
49c7303f AF	275	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
86887f8e	276
49c7303f	277	/* SMSC922x Ethernet */
86887f8e	278	#if defined(CONFIG_CMD_NET)
86887f8e	279	#define CONFIG_SMC911X
1e1acc76	280	#define CONFIG_SMC911X_32_BIT
86887f8e	281	#define CONFIG_SMC911X_BASE 0x08000000
86887f8e PB	282	#endif /* (CONFIG_CMD_NET) */
86887f8e PB	283
49c7303f AF	284	/* Defines for SPL */
	285
	286	#define CONFIG_SPL_OMAP3_ID_NAND
	287
	288	/* NAND: SPL falcon mode configs */
	289	#ifdef CONFIG_SPL_OS_BOOT
	290	#define CONFIG_CMD_SPL_NAND_OFS 0x240000
	291	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
	292	#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
	293	#endif
	294
86887f8e	295	#endif /* __CONFIG_H */