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84d7a017 MJ |
1 | /* |
2 | * MATRIX VISION GmbH mvBlueLYNX-X | |
3 | * | |
4 | * Derived from omap3_beagle.h: | |
5 | * (C) Copyright 2006-2008 | |
6 | * Texas Instruments. | |
7 | * Richard Woodruff <r-woodruff2@ti.com> | |
8 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
9 | * | |
10 | * Configuration settings for the TI OMAP3530 Beagle board. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | */ | |
37 | #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ | |
38 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
39 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
84d7a017 MJ |
40 | #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ |
41 | #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX | |
308252ad | 42 | #define CONFIG_OMAP_GPIO |
84d7a017 MJ |
43 | |
44 | #define CONFIG_SDRC /* The chip has SDRC controller */ | |
45 | ||
46 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
47 | #include <asm/arch/omap3.h> | |
48 | ||
49 | /* | |
50 | * Display CPU and Board information | |
51 | */ | |
52 | #define CONFIG_DISPLAY_CPUINFO 1 | |
53 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
54 | ||
55 | /* Clock Defines */ | |
56 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
57 | #define V_SCLK (V_OSCK >> 1) | |
58 | ||
84d7a017 MJ |
59 | #define CONFIG_MISC_INIT_R |
60 | ||
61 | #define CONFIG_OF_LIBFDT 1 | |
62 | ||
63 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
64 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
65 | #define CONFIG_INITRD_TAG 1 | |
66 | #define CONFIG_REVISION_TAG 1 | |
67 | #define CONFIG_SERIAL_TAG 1 | |
68 | ||
69 | /* | |
70 | * Size of malloc() pool | |
71 | */ | |
72 | #define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */ | |
73 | /* Sector */ | |
74 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
75 | ||
76 | /* | |
77 | * Hardware drivers | |
78 | */ | |
79 | ||
80 | /* | |
81 | * NS16550 Configuration | |
82 | */ | |
83 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
84 | ||
85 | #define CONFIG_SYS_NS16550 | |
86 | #define CONFIG_SYS_NS16550_SERIAL | |
87 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
88 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
89 | ||
90 | /* | |
91 | * select serial console configuration | |
92 | */ | |
93 | #define CONFIG_CONS_INDEX 3 | |
94 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
95 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
96 | ||
97 | #define CONFIG_BAUDRATE 115200 | |
98 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
99 | 115200} | |
100 | #define CONFIG_GENERIC_MMC 1 | |
101 | #define CONFIG_MMC 1 | |
102 | #define CONFIG_OMAP_HSMMC 1 | |
103 | #define CONFIG_DOS_PARTITION 1 | |
104 | ||
84d7a017 MJ |
105 | /* USB */ |
106 | #define CONFIG_MUSB_UDC 1 | |
107 | #define CONFIG_USB_OMAP3 1 | |
108 | #define CONFIG_TWL4030_USB 1 | |
109 | ||
110 | /* USB device configuration */ | |
111 | #define CONFIG_USB_DEVICE 1 | |
112 | #define CONFIG_USB_TTY 1 | |
113 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
114 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 | |
115 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 | |
116 | #define CONFIG_USBD_VENDORID 0x164c | |
117 | #define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201 | |
118 | #define CONFIG_USBD_PRODUCTID_CDCACM 0x0201 | |
119 | #define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH" | |
120 | #define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X" | |
121 | ||
122 | /* no FLASH available */ | |
123 | #define CONFIG_SYS_NO_FLASH | |
124 | ||
125 | /* commands to include */ | |
126 | #include <config_cmd_default.h> | |
127 | ||
128 | #define CONFIG_CMD_CACHE | |
129 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
130 | #define CONFIG_CMD_FAT /* FAT support */ | |
131 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
132 | #define CONFIG_CMD_MMC /* MMC support */ | |
133 | #define CONFIG_CMD_EEPROM | |
134 | #define CONFIG_CMD_IMI /* iminfo */ | |
135 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
136 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
137 | #define CONFIG_CMD_NFS /* NFS support */ | |
138 | #define CONFIG_CMD_DHCP | |
139 | #define CONFIG_CMD_PING | |
140 | #define CONFIG_CMD_FPGA | |
141 | ||
142 | #define CONFIG_HARD_I2C 1 | |
143 | #define CONFIG_SYS_I2C_SPEED 100000 | |
144 | #define CONFIG_SYS_I2C_SLAVE 0 | |
145 | #define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */ | |
146 | #define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */ | |
147 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 | |
148 | #define CONFIG_I2C_MULTI_BUS 1 | |
149 | ||
150 | /* | |
151 | * TWL4030 | |
152 | */ | |
153 | #define CONFIG_TWL4030_POWER 1 | |
154 | ||
155 | /* Environment information */ | |
156 | #undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ | |
157 | #define CONFIG_BOOTDELAY 3 | |
158 | ||
159 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
160 | "loadaddr=0x82000000\0" \ | |
161 | "usbtty=cdc_acm\0" \ | |
162 | "console=ttyO2,115200n8\0" \ | |
163 | "mpurate=600\0" \ | |
164 | "vram=12M\0" \ | |
165 | "dvimode=1024x768-24@60\0" \ | |
166 | "defaultdisplay=dvi\0" \ | |
167 | "fpgafilename=mvbluelynx_x.rbf\0" \ | |
168 | "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \ | |
169 | "fpga load 0 ${loadaddr} ${filesize}; " \ | |
170 | "fi;\0" \ | |
171 | "mmcdev=0\0" \ | |
172 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
173 | "mmcrootfstype=ext3 rootwait\0" \ | |
174 | "mmcargs=setenv bootargs console=${console} " \ | |
175 | "mpurate=${mpurate} " \ | |
176 | "vram=${vram} " \ | |
177 | "omapfb.mode=dvi:${dvimode} " \ | |
178 | "omapfb.debug=y " \ | |
179 | "omapdss.def_disp=${defaultdisplay} " \ | |
180 | "root=${mmcroot} " \ | |
181 | "rootfstype=${mmcrootfstype} " \ | |
182 | "${cmdline_suffix}\0" \ | |
183 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ | |
184 | "importbootenv=echo Importing environment from mmc ...; " \ | |
185 | "env import -t $loadaddr $filesize\0" \ | |
186 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
187 | "mmcboot=echo Booting from mmc ...; " \ | |
188 | "run mmcargs; " \ | |
189 | "bootm ${loadaddr}\0" \ | |
190 | "mmcbootcmd= " \ | |
191 | "echo Trying mmc${mmcdev}; " \ | |
192 | "mmc dev ${mmcdev}; " \ | |
193 | "if mmc rescan; then " \ | |
194 | "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \ | |
195 | "echo SD/MMC found on device ${mmcdev};" \ | |
196 | "if run loadbootenv; then " \ | |
197 | "echo Loading boot environment from mmc${mmcdev}; " \ | |
198 | "run importbootenv; " \ | |
199 | "fi;" \ | |
200 | "run loadfpga; " \ | |
201 | "if test -n $uenvcmd; then " \ | |
202 | "echo Running uenvcmd ...;" \ | |
203 | "run uenvcmd;" \ | |
204 | "fi;" \ | |
205 | "if run loaduimage; then " \ | |
206 | "run mmcboot; " \ | |
207 | "fi;" \ | |
208 | "fi\0" | |
209 | ||
210 | #define CONFIG_BOOTCOMMAND \ | |
211 | "setenv mmcdev 1;" \ | |
212 | "run mmcbootcmd || " \ | |
213 | "setenv mmcdev 0;" \ | |
214 | "run mmcbootcmd" | |
215 | ||
216 | ||
217 | #define CONFIG_AUTO_COMPLETE 1 | |
218 | /* | |
219 | * Miscellaneous configurable options | |
220 | */ | |
221 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
222 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
84d7a017 MJ |
223 | #define CONFIG_SYS_PROMPT "mvblx # " |
224 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
225 | /* Print Buffer Size */ | |
226 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
227 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
228 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
229 | /* Boot Argument Buffer Size */ | |
230 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
231 | ||
232 | #define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */ | |
233 | #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */ | |
234 | #define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */ | |
235 | #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ | |
236 | ||
237 | /* default load address */ | |
238 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) | |
239 | ||
240 | /* | |
241 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
242 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
243 | * This rate is divided by a local divisor. | |
244 | */ | |
245 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
246 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
247 | #define CONFIG_SYS_HZ 1000 | |
248 | ||
84d7a017 MJ |
249 | /*----------------------------------------------------------------------- |
250 | * Physical Memory Map | |
251 | */ | |
252 | #define CONFIG_NR_DRAM_BANKS 1 | |
253 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
254 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ | |
255 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
256 | ||
84d7a017 MJ |
257 | #define CONFIG_ENV_IS_NOWHERE 1 |
258 | ||
259 | /*---------------------------------------------------------------------------- | |
260 | * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family) | |
261 | *---------------------------------------------------------------------------- | |
262 | */ | |
263 | #if defined(CONFIG_CMD_NET) | |
84d7a017 MJ |
264 | #define CONFIG_SMC911X 1 |
265 | #define CONFIG_SMC911X_32_BIT | |
266 | #define CONFIG_SMC911X_BASE 0x2C000000 | |
267 | #endif /* (CONFIG_CMD_NET) */ | |
268 | ||
269 | #define CONFIG_FPGA_COUNT 1 | |
270 | #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 | |
271 | #define CONFIG_FPGA_ALTERA | |
272 | #define CONFIG_FPGA_CYCLON2 | |
273 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK | |
274 | #define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE | |
275 | ||
276 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */ | |
277 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
278 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */ | |
279 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
280 | #define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */ | |
281 | #define CONFIG_ID_EEPROM | |
282 | #define CONFIG_SYS_EEPROM_BUS_NUM 2 | |
283 | ||
284 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
285 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
286 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
287 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
288 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
289 | GENERATED_GBL_DATA_SIZE) | |
290 | ||
291 | #define CONFIG_OMAP3_SPI | |
292 | ||
8e40852f A |
293 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
294 | ||
84d7a017 | 295 | #endif /* __CONFIG_H */ |