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376aee78 TR |
1 | /* |
2 | * (C) Copyright 2006-2009 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * Nishanth Menon <nm@ti.com> | |
7 | * Tom Rix <Tom.Rix@windriver.com> | |
8 | * | |
9 | * Configuration settings for the TI OMAP3430 Zoom II board. | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
376aee78 TR |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
376aee78 TR |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | */ | |
376aee78 TR |
20 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
21 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
376aee78 | 22 | #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ |
308252ad | 23 | #define CONFIG_OMAP_GPIO |
376aee78 | 24 | |
cae377b5 VH |
25 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
26 | ||
376aee78 TR |
27 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
28 | #include <asm/arch/omap3.h> | |
29 | ||
3962c4f9 DB |
30 | /* |
31 | * Display CPU and Board information | |
32 | */ | |
33 | #define CONFIG_DISPLAY_CPUINFO 1 | |
34 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
35 | ||
376aee78 TR |
36 | /* Clock Defines */ |
37 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
38 | #define V_SCLK (V_OSCK >> 1) | |
39 | ||
376aee78 TR |
40 | #define CONFIG_MISC_INIT_R |
41 | ||
42 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
43 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
44 | #define CONFIG_INITRD_TAG 1 | |
45 | #define CONFIG_REVISION_TAG 1 | |
46 | ||
2fa8ca98 GL |
47 | #define CONFIG_OF_LIBFDT 1 |
48 | ||
376aee78 TR |
49 | /* |
50 | * Size of malloc() pool | |
51 | */ | |
9c44ddcc | 52 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
376aee78 | 53 | /* Sector */ |
9c44ddcc | 54 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
376aee78 TR |
55 | /* |
56 | * Hardware drivers | |
57 | */ | |
58 | ||
59 | /* | |
60 | * NS16550 Configuration | |
660888b7 | 61 | * Zoom2 uses the TL16CP754C on the debug board |
376aee78 | 62 | */ |
660888b7 TR |
63 | /* |
64 | * 0 - 1 : first USB with respect to the left edge of the debug board | |
65 | * 2 - 3 : second USB with respect to the left edge of the debug board | |
66 | */ | |
425101e1 | 67 | #define ZOOM2_DEFAULT_SERIAL_DEVICE 0 |
660888b7 TR |
68 | |
69 | #define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ | |
376aee78 TR |
70 | |
71 | #define CONFIG_SYS_NS16550 | |
660888b7 | 72 | #define CONFIG_SYS_NS16550_REG_SIZE (-2) |
376aee78 | 73 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
660888b7 TR |
74 | #define CONFIG_BAUDRATE 115200 |
75 | #define CONFIG_SYS_BAUDRATE_TABLE {115200} | |
376aee78 TR |
76 | |
77 | /* allow to overwrite serial and ethaddr */ | |
78 | #define CONFIG_ENV_OVERWRITE | |
660888b7 | 79 | |
cfc4384c | 80 | #define CONFIG_GENERIC_MMC 1 |
376aee78 | 81 | #define CONFIG_MMC 1 |
cfc4384c | 82 | #define CONFIG_OMAP_HSMMC 1 |
376aee78 | 83 | #define CONFIG_DOS_PARTITION 1 |
30563a04 | 84 | |
83ae698f TR |
85 | /* Status LED */ |
86 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
87 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
88 | #define STATUS_LED_BLUE 0 | |
89 | #define STATUS_LED_RED 1 | |
90 | /* Blue */ | |
91 | #define STATUS_LED_BIT STATUS_LED_BLUE | |
92 | #define STATUS_LED_STATE STATUS_LED_ON | |
93 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
94 | /* Red */ | |
95 | #define STATUS_LED_BIT1 STATUS_LED_RED | |
96 | #define STATUS_LED_STATE1 STATUS_LED_OFF | |
97 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
98 | /* Optional value */ | |
99 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
100 | ||
0c9520ef TR |
101 | /* GPIO banks */ |
102 | #ifdef CONFIG_STATUS_LED | |
103 | #define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ | |
104 | #define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ | |
105 | #endif | |
106 | #define CONFIG_OMAP3_GPIO_3 /* board revision */ | |
107 | #define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ | |
108 | ||
2ec1abea TR |
109 | /* USB */ |
110 | #define CONFIG_MUSB_UDC 1 | |
111 | #define CONFIG_USB_OMAP3 1 | |
112 | #define CONFIG_TWL4030_USB 1 | |
113 | ||
114 | /* USB device configuration */ | |
115 | #define CONFIG_USB_DEVICE 1 | |
116 | #define CONFIG_USB_TTY 1 | |
117 | /* Change these to suit your needs */ | |
118 | #define CONFIG_USBD_VENDORID 0x0451 | |
119 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
120 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
121 | #define CONFIG_USBD_PRODUCT_NAME "Zoom2" | |
122 | ||
376aee78 TR |
123 | /* commands to include */ |
124 | #include <config_cmd_default.h> | |
125 | ||
126 | #define CONFIG_CMD_FAT /* FAT support */ | |
127 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
128 | #define CONFIG_CMD_MMC /* MMC support */ | |
129 | #define CONFIG_CMD_NAND /* NAND support */ | |
130 | #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ | |
131 | ||
132 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
133 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
134 | #undef CONFIG_CMD_IMI /* iminfo */ | |
135 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
136 | #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
137 | #undef CONFIG_CMD_NFS /* NFS support */ | |
138 | ||
139 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 140 | #define CONFIG_HARD_I2C 1 |
376aee78 TR |
141 | #define CONFIG_SYS_I2C_SPEED 100000 |
142 | #define CONFIG_SYS_I2C_SLAVE 1 | |
376aee78 TR |
143 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
144 | ||
cd782635 TR |
145 | /* |
146 | * TWL4030 | |
147 | */ | |
148 | #define CONFIG_TWL4030_POWER 1 | |
2c155130 | 149 | #define CONFIG_TWL4030_LED 1 |
cd782635 | 150 | |
376aee78 TR |
151 | /* |
152 | * Board NAND Info. | |
153 | */ | |
154 | #define CONFIG_NAND_OMAP_GPMC | |
155 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
156 | /* to access nand */ | |
157 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
158 | /* to access nand at */ | |
159 | /* CS0 */ | |
160 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
161 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
162 | ||
163 | /* Environment information */ | |
164 | #define CONFIG_BOOTDELAY 10 | |
165 | ||
2ec1abea TR |
166 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
167 | "usbtty=cdc_acm\0" \ | |
168 | ||
998f4caf DB |
169 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
170 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
171 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
172 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
173 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
174 | GENERATED_GBL_DATA_SIZE) | |
376aee78 TR |
175 | /* |
176 | * Miscellaneous configurable options | |
177 | */ | |
178 | ||
179 | #define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " | |
180 | #define CONFIG_SYS_LONGHELP | |
f62b1257 | 181 | #define CONFIG_SYS_CBSIZE 512 |
376aee78 TR |
182 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
183 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
184 | #define CONFIG_SYS_MAXARGS 16 | |
185 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
186 | /* Memtest from start of memory to 31MB */ | |
187 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
188 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) | |
189 | /* The default load address is the start of memory */ | |
190 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) | |
191 | /* everything, incl board info, in Hz */ | |
192 | #undef CONFIG_SYS_CLKS_IN_HZ | |
193 | /* | |
194 | * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by | |
195 | * 32KHz clk, or from external sig. This rate is divided by a local divisor. | |
196 | */ | |
197 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
198 | #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ | |
199 | #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) | |
200 | ||
376aee78 TR |
201 | /*----------------------------------------------------------------------- |
202 | * Physical Memory Map | |
203 | */ | |
204 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
205 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
376aee78 TR |
206 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
207 | ||
376aee78 TR |
208 | /*----------------------------------------------------------------------- |
209 | * FLASH and environment organization | |
210 | */ | |
211 | ||
212 | /* **** PISMO SUPPORT *** */ | |
213 | ||
214 | /* Configure the PISMO */ | |
215 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
216 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
217 | ||
9c44ddcc | 218 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
376aee78 | 219 | |
6cbec7b3 LC |
220 | #if defined(CONFIG_CMD_NAND) |
221 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
222 | #endif | |
376aee78 TR |
223 | |
224 | /* Monitor at start of flash */ | |
225 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
226 | ||
227 | #define CONFIG_ENV_IS_IN_NAND 1 | |
228 | #define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ | |
229 | ||
6cbec7b3 LC |
230 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
231 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
376aee78 TR |
232 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
233 | ||
8e40852f A |
234 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
235 | ||
376aee78 | 236 | #endif /* __CONFIG_H */ |