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a9c1c042 S |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments Incorporated. | |
4 | * Sricharan R <r.sricharan@ti.com> | |
5 | * | |
6 | * Derived from OMAP4 done by: | |
7 | * Aneesh V <aneesh@ti.com> | |
8 | * | |
9 | * Configuration settings for the TI EVM5430 board. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | */ | |
36 | #define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ | |
37 | #define CONFIG_OMAP /* in a TI OMAP core */ | |
38 | #define CONFIG_OMAP54XX /* which is a 54XX */ | |
39 | #define CONFIG_OMAP5430 /* which is in a 5430 */ | |
40 | #define CONFIG_5430EVM /* working with EVM */ | |
308252ad | 41 | #define CONFIG_OMAP_GPIO |
a9c1c042 S |
42 | |
43 | /* Get CPU defs */ | |
44 | #include <asm/arch/cpu.h> | |
45 | #include <asm/arch/omap.h> | |
46 | ||
47 | /* Display CPU and Board Info */ | |
48 | #define CONFIG_DISPLAY_CPUINFO | |
49 | #define CONFIG_DISPLAY_BOARDINFO | |
50 | ||
51 | /* Clock Defines */ | |
7a4bf209 | 52 | #define V_OSCK 19200000 /* Clock output from T2 */ |
a9c1c042 S |
53 | #define V_SCLK V_OSCK |
54 | ||
a9c1c042 S |
55 | #define CONFIG_MISC_INIT_R |
56 | ||
57 | #define CONFIG_OF_LIBFDT | |
fe8f1372 | 58 | #define CONFIG_CMD_BOOTZ |
a9c1c042 S |
59 | |
60 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
61 | #define CONFIG_SETUP_MEMORY_TAGS | |
62 | #define CONFIG_INITRD_TAG | |
63 | ||
64 | /* | |
65 | * Size of malloc() pool | |
66 | * Total Size Environment - 128k | |
67 | * Malloc - add 256k | |
68 | */ | |
69 | #define CONFIG_ENV_SIZE (128 << 10) | |
70 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) | |
71 | /* Vector Base */ | |
72 | #define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE | |
73 | ||
74 | /* | |
75 | * Hardware drivers | |
76 | */ | |
77 | ||
78 | /* | |
79 | * serial port - NS16550 compatible | |
80 | */ | |
81 | #define V_NS16550_CLK 48000000 | |
82 | ||
83 | #define CONFIG_SYS_NS16550 | |
84 | #define CONFIG_SYS_NS16550_SERIAL | |
85 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
86 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
87 | #define CONFIG_CONS_INDEX 3 | |
88 | #define CONFIG_SYS_NS16550_COM3 UART3_BASE | |
89 | ||
90 | #define CONFIG_BAUDRATE 115200 | |
91 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
92 | 115200} | |
93 | /* I2C */ | |
94 | #define CONFIG_HARD_I2C | |
95 | #define CONFIG_SYS_I2C_SPEED 100000 | |
96 | #define CONFIG_SYS_I2C_SLAVE 1 | |
97 | #define CONFIG_DRIVER_OMAP34XX_I2C | |
98 | #define CONFIG_I2C_MULTI_BUS | |
99 | ||
21144298 S |
100 | /* TWL6035 */ |
101 | #ifndef CONFIG_SPL_BUILD | |
102 | #define CONFIG_TWL6035_POWER | |
103 | #endif | |
104 | ||
a9c1c042 S |
105 | /* MMC */ |
106 | #define CONFIG_GENERIC_MMC | |
107 | #define CONFIG_MMC | |
108 | #define CONFIG_OMAP_HSMMC | |
109 | #define CONFIG_DOS_PARTITION | |
110 | ||
111 | /* MMC ENV related defines */ | |
112 | #define CONFIG_ENV_IS_IN_MMC | |
113 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ | |
114 | #define CONFIG_ENV_OFFSET 0xE0000 | |
328aecaf | 115 | #define CONFIG_CMD_SAVEENV |
a9c1c042 | 116 | |
a9c1c042 S |
117 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
118 | ||
119 | /* Flash */ | |
120 | #define CONFIG_SYS_NO_FLASH | |
121 | ||
122 | /* Cache */ | |
123 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
124 | #define CONFIG_SYS_CACHELINE_SHIFT 6 | |
125 | ||
126 | /* commands to include */ | |
127 | #include <config_cmd_default.h> | |
128 | ||
129 | /* Enabled commands */ | |
130 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
131 | #define CONFIG_CMD_FAT /* FAT support */ | |
132 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
133 | #define CONFIG_CMD_MMC /* MMC support */ | |
134 | #define CONFIG_CMD_SAVEENV | |
135 | ||
136 | /* Disabled commands */ | |
137 | #undef CONFIG_CMD_NET | |
138 | #undef CONFIG_CMD_NFS | |
139 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
140 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
141 | ||
142 | /* | |
143 | * Environment setup | |
144 | */ | |
145 | ||
146 | #define CONFIG_BOOTDELAY 3 | |
147 | ||
148 | #define CONFIG_ENV_OVERWRITE | |
149 | ||
150 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
151 | "loadaddr=0x82000000\0" \ | |
7a4bf209 | 152 | "console=ttyO2,115200n8\0" \ |
a9c1c042 S |
153 | "usbtty=cdc_acm\0" \ |
154 | "vram=16M\0" \ | |
155 | "mmcdev=0\0" \ | |
156 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
157 | "mmcrootfstype=ext3 rootwait\0" \ | |
158 | "mmcargs=setenv bootargs console=${console} " \ | |
159 | "vram=${vram} " \ | |
160 | "root=${mmcroot} " \ | |
161 | "rootfstype=${mmcrootfstype}\0" \ | |
162 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
163 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ | |
164 | "source ${loadaddr}\0" \ | |
165 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
166 | "mmcboot=echo Booting from mmc${mmcdev} ...; " \ | |
167 | "run mmcargs; " \ | |
168 | "bootm ${loadaddr}\0" \ | |
169 | ||
170 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 171 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
a9c1c042 S |
172 | "if run loadbootscript; then " \ |
173 | "run bootscript; " \ | |
174 | "else " \ | |
175 | "if run loaduimage; then " \ | |
176 | "run mmcboot; " \ | |
177 | "fi; " \ | |
178 | "fi; " \ | |
179 | "fi" | |
180 | ||
181 | #define CONFIG_AUTO_COMPLETE 1 | |
182 | ||
183 | /* | |
184 | * Miscellaneous configurable options | |
185 | */ | |
186 | ||
187 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
188 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
a9c1c042 S |
189 | #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " |
190 | #define CONFIG_SYS_CBSIZE 256 | |
191 | /* Print Buffer Size */ | |
192 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
193 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
194 | #define CONFIG_SYS_MAXARGS 16 | |
195 | /* Boot Argument Buffer Size */ | |
196 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
197 | ||
198 | /* | |
199 | * memtest setup | |
200 | */ | |
201 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
202 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) | |
203 | ||
204 | /* Default load address */ | |
205 | #define CONFIG_SYS_LOAD_ADDR 0x80000000 | |
206 | ||
207 | /* Use General purpose timer 1 */ | |
208 | #define CONFIG_SYS_TIMERBASE GPT2_BASE | |
209 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
210 | #define CONFIG_SYS_HZ 1000 | |
211 | ||
a9c1c042 S |
212 | /* |
213 | * SDRAM Memory Map | |
214 | * Even though we use two CS all the memory | |
215 | * is mapped to one contiguous block | |
216 | */ | |
217 | #define CONFIG_NR_DRAM_BANKS 1 | |
218 | ||
219 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
41aebf81 | 220 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
a9c1c042 S |
221 | GENERATED_GBL_DATA_SIZE) |
222 | ||
223 | #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS | |
224 | ||
225 | /* Defines for SDRAM init */ | |
226 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS | |
227 | #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION | |
228 | #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS | |
229 | #endif | |
230 | ||
231 | /* Defines for SPL */ | |
232 | #define CONFIG_SPL | |
47f7bcae | 233 | #define CONFIG_SPL_FRAMEWORK |
7a4bf209 S |
234 | #define CONFIG_SPL_TEXT_BASE 0x40300350 |
235 | #define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ | |
41aebf81 | 236 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
861a86f4 | 237 | #define CONFIG_SPL_DISPLAY_PRINT |
a9c1c042 | 238 | |
a9c1c042 S |
239 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ |
240 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
241 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
242 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" | |
243 | ||
244 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
245 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
246 | #define CONFIG_SPL_I2C_SUPPORT | |
247 | #define CONFIG_SPL_MMC_SUPPORT | |
248 | #define CONFIG_SPL_FAT_SUPPORT | |
249 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
250 | #define CONFIG_SPL_SERIAL_SUPPORT | |
d1df0fd3 | 251 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
a9c1c042 S |
252 | |
253 | /* | |
a9c1c042 | 254 | * 64 bytes before this address should be set aside for u-boot.img's |
f6ddfdd3 | 255 | * header. That is 80E7FFC0--0x80E80000 should not be used for any |
a9c1c042 S |
256 | * other needs. |
257 | */ | |
f6ddfdd3 A |
258 | #define CONFIG_SYS_TEXT_BASE 0x80E80000 |
259 | ||
260 | /* | |
261 | * BSS and malloc area 64MB into memory to allow enough | |
262 | * space for the kernel at the beginning of memory | |
263 | */ | |
264 | #define CONFIG_SPL_BSS_START_ADDR 0x84000000 | |
265 | #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ | |
266 | #define CONFIG_SYS_SPL_MALLOC_START 0x84100000 | |
267 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ | |
3fcdd4a5 | 268 | #define CONFIG_SPL_GPIO_SUPPORT |
a9c1c042 S |
269 | |
270 | #endif /* __CONFIG_H */ |