Move CONFIG_OF_LIBFDT to Kconfig
[people/ms/u-boot.git] / include / configs / omapl138_lcdk.h
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1/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
5b8031cc 8 * SPDX-License-Identifier: GPL-2.0
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Board
16 */
17#define CONFIG_DRIVER_TI_EMAC
18#undef CONFIG_USE_SPIFLASH
19#undef CONFIG_SYS_USE_NOR
20#define CONFIG_USE_NAND
21
22/*
23 * SoC Configuration
24 */
25#define CONFIG_MACH_OMAPL138_LCDK
26#define CONFIG_ARM926EJS /* arm926ejs CPU core */
27#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
28#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
29#define CONFIG_SYS_OSCIN_FREQ 24000000
30#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
31#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
32#define CONFIG_SYS_HZ 1000
33#define CONFIG_SKIP_LOWLEVEL_INIT
34#define CONFIG_SYS_TEXT_BASE 0xc1080000
35
36/*
37 * Memory Info
38 */
39#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
40#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
41#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
42#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
43
44/* memtest start addr */
45#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
46
47/* memtest will be run on 16MB */
48#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
49
50#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
51#define CONFIG_STACKSIZE (256*1024) /* regular stack */
52
53#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
54 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
55 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
56 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
57 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
58 DAVINCI_SYSCFG_SUSPSRC_I2C)
59
60/*
61 * PLL configuration
62 */
63#define CONFIG_SYS_DV_CLKMODE 0
64#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
65#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
66#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
67#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
68#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
69#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
70#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
71#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
72
73#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
74#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
75#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
76#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
77
78#define CONFIG_SYS_DA850_PLL0_PLLM 24
79#define CONFIG_SYS_DA850_PLL1_PLLM 21
80
81/*
82 * Serial Driver info
83 */
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84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
86#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
87#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
88#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
89#define CONFIG_BAUDRATE 115200 /* Default baud rate */
90#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
91
92#define CONFIG_SPI
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93#define CONFIG_DAVINCI_SPI
94#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
95#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
96#define CONFIG_SF_DEFAULT_SPEED 30000000
97#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
98
99#ifdef CONFIG_USE_SPIFLASH
100#define CONFIG_SPL_SPI_SUPPORT
101#define CONFIG_SPL_SPI_FLASH_SUPPORT
102#define CONFIG_SPL_SPI_LOAD
103#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
104#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
105#endif
106
107/*
108 * I2C Configuration
109 */
110#define CONFIG_SYS_I2C
111#define CONFIG_SYS_I2C_DAVINCI
112#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
113#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
114#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
115
116/*
117 * Flash & Environment
118 */
119#ifdef CONFIG_USE_NAND
120#undef CONFIG_ENV_IS_IN_FLASH
121#define CONFIG_NAND_DAVINCI
122#define CONFIG_SYS_NO_FLASH
123#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
124#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
125#define CONFIG_ENV_SIZE (128 << 9)
126#define CONFIG_SYS_NAND_USE_FLASH_BBT
127#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
128#define CONFIG_SYS_NAND_PAGE_2K
129#define CONFIG_SYS_NAND_BUSWIDTH_16_BIT
130#define CONFIG_SYS_NAND_CS 3
131#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
132#define CONFIG_SYS_CLE_MASK 0x10
133#define CONFIG_SYS_ALE_MASK 0x8
134#undef CONFIG_SYS_NAND_HW_ECC
135#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
136#define NAND_MAX_CHIPS 1
137#endif
138
139#ifdef CONFIG_SYS_USE_NOR
140#define CONFIG_ENV_IS_IN_FLASH
141#undef CONFIG_SYS_NO_FLASH
142#define CONFIG_FLASH_CFI_DRIVER
143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_SYS_FLASH_PROTECTION
145#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
146#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
147#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
148#define CONFIG_ENV_SIZE (128 << 10)
149#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
150#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
151#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
152 + 3)
153#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
154#endif
155
156#ifdef CONFIG_USE_SPIFLASH
157#undef CONFIG_ENV_IS_IN_FLASH
158#undef CONFIG_ENV_IS_IN_NAND
159#define CONFIG_ENV_IS_IN_SPI_FLASH
160#define CONFIG_ENV_SIZE (64 << 10)
161#define CONFIG_ENV_OFFSET (256 << 10)
162#define CONFIG_ENV_SECT_SIZE (64 << 10)
163#define CONFIG_SYS_NO_FLASH
164#endif
165
166/*
167 * Network & Ethernet Configuration
168 */
169#ifdef CONFIG_DRIVER_TI_EMAC
170#define CONFIG_EMAC_MDIO_PHY_NUM 7
171#define CONFIG_MII
172#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
173#define CONFIG_BOOTP_DEFAULT
174#define CONFIG_BOOTP_DNS
175#define CONFIG_BOOTP_DNS2
176#define CONFIG_BOOTP_SEND_HOSTNAME
177#define CONFIG_NET_RETRY_COUNT 10
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178#endif
179
180/*
181 * U-Boot general configuration
182 */
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183#define CONFIG_MISC_INIT_R
184#define CONFIG_BOARD_EARLY_INIT_F
185#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
187#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
188#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
189#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
190#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
191#define CONFIG_VERSION_VARIABLE
192#define CONFIG_AUTO_COMPLETE
193#define CONFIG_SYS_HUSH_PARSER
194#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
195#define CONFIG_CMDLINE_EDITING
196#define CONFIG_SYS_LONGHELP
197#define CONFIG_CRC32_VERIFY
198#define CONFIG_MX_CYCLIC
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199
200/*
201 * Linux Information
202 */
203#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
204#define CONFIG_CMDLINE_TAG
205#define CONFIG_REVISION_TAG
206#define CONFIG_SETUP_MEMORY_TAGS
207#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
208#define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
209#define CONFIG_BOOTDELAY 3
210
211/*
212 * U-Boot commands
213 */
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214#define CONFIG_CMD_ENV
215#define CONFIG_CMD_ASKENV
216#define CONFIG_CMD_DHCP
217#define CONFIG_CMD_DIAG
218#define CONFIG_CMD_MII
219#define CONFIG_CMD_PING
220#define CONFIG_CMD_SAVES
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221#ifdef CONFIG_CMD_BDI
222#define CONFIG_CLOCKS
223#endif
224
225#ifndef CONFIG_DRIVER_TI_EMAC
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226#undef CONFIG_CMD_DHCP
227#undef CONFIG_CMD_MII
228#undef CONFIG_CMD_PING
229#endif
230
231#ifdef CONFIG_USE_NAND
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232#define CONFIG_CMD_NAND
233
234#define CONFIG_CMD_MTDPARTS
235#define CONFIG_MTD_DEVICE
236#define CONFIG_MTD_PARTITIONS
237#define CONFIG_LZO
238#define CONFIG_RBTREE
239#define CONFIG_CMD_UBI
240#define CONFIG_CMD_UBIFS
241#endif
242
243#ifdef CONFIG_USE_SPIFLASH
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244#define CONFIG_CMD_SPI
245#define CONFIG_CMD_SF
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246#endif
247
248#if !defined(CONFIG_USE_NAND) && \
249 !defined(CONFIG_SYS_USE_NOR) && \
250 !defined(CONFIG_USE_SPIFLASH)
251#define CONFIG_ENV_IS_NOWHERE
252#define CONFIG_SYS_NO_FLASH
253#define CONFIG_ENV_SIZE (16 << 10)
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254#undef CONFIG_CMD_ENV
255#endif
256
257/* SD/MMC */
258#define CONFIG_MMC
259#define CONFIG_GENERIC_MMC
260#define CONFIG_DAVINCI_MMC
261
262#ifdef CONFIG_MMC
263#define CONFIG_DOS_PARTITION
264#define CONFIG_CMD_EXT2
265#define CONFIG_CMD_FAT
266#define CONFIG_CMD_MMC
267#undef CONFIG_ENV_IS_IN_MMC
268#endif
269
270#ifdef CONFIG_ENV_IS_IN_MMC
271#undef CONFIG_ENV_SIZE
272#undef CONFIG_ENV_OFFSET
273#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
274#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
275#undef CONFIG_ENV_IS_IN_FLASH
276#undef CONFIG_ENV_IS_IN_NAND
277#undef CONFIG_ENV_IS_IN_SPI_FLASH
278#endif
279
280#ifndef CONFIG_DIRECT_NOR_BOOT
281/* defines for SPL */
282#define CONFIG_SPL_FRAMEWORK
283#define CONFIG_SPL_BOARD_INIT
284#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
285 CONFIG_SYS_MALLOC_LEN)
286#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
287#define CONFIG_SPL_SERIAL_SUPPORT
288#define CONFIG_SPL_LIBCOMMON_SUPPORT
289#define CONFIG_SPL_LIBGENERIC_SUPPORT
290#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
291#define CONFIG_SPL_STACK 0x8001ff00
292#define CONFIG_SPL_TEXT_BASE 0x80000000
293#define CONFIG_SPL_MAX_FOOTPRINT 32768
294#define CONFIG_SPL_PAD_TO 32768
295#endif
296
297/* additions for new relocation code, must added to all boards */
298#define CONFIG_SYS_SDRAM_BASE 0xc0000000
299#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
300 GENERATED_GBL_DATA_SIZE)
301#endif /* __CONFIG_H */