[people/ms/u-boot.git] / include / configs / omapl138_lcdk.h

/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
#define CONFIG_DRIVER_TI_EMAC
#undef CONFIG_USE_SPIFLASH
#undef	CONFIG_SYS_USE_NOR
#define	CONFIG_USE_NAND

/*
 * SoC Configuration
 */
#define CONFIG_MACH_OMAPL138_LCDK
#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ			1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE		0xc1080000

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)

#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE	(256*1024) /* regular stack */

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */
#define CONFIG_SYS_DV_CLKMODE          0
#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005

#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8003

#define CONFIG_SYS_DA850_PLL0_PLLM     37
#define CONFIG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
	(10 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
	(2 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_SPI
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED

#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
#endif

/*
 * I2C Configuration
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20

/*
 * Flash & Environment
 */
#ifdef CONFIG_USE_NAND
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE			(128 << 9)
#define	CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define	CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE	0x10
#define CONFIG_SYS_NAND_MASK_ALE	0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_LOAD
#endif

#ifdef CONFIG_SYS_USE_NOR
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
#define CONFIG_ENV_SIZE			(128 << 10)
#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	       + 3)
#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
#endif

#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			(64 << 10)
#define CONFIG_ENV_OFFSET		(256 << 10)
#define CONFIG_ENV_SECT_SIZE		(64 << 10)
#endif

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM	7
#define CONFIG_MII
#undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE		"zImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
#define CONFIG_BOOTCOMMAND \
	"if mmc rescan; then " \
		"run mmcboot; " \
	"else " \
		"run spiboot; " \
	"fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtaddr=0xc0600000\0" \
	"fdtfile=da850-lcdk.dtb\0" \
	"fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \
	"mmcboot=" \
		"if fatload mmc 0 0xc0600000 boot.scr; then " \
			"source 0xc0600000; " \
		"else " \
			"fatload mmc 0 0xc0700000 " \
				__stringify(CONFIG_BOOTFILE) "; " \
			"fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
			"run fdtboot; " \
		"fi;\0" \
	"spiboot=" \
		"sf probe 0; " \
		"sf read 0xc0700000 0x80000 0x220000; " \
		"bootz 0xc0700000;\0"

/*
 * U-Boot commands
 */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#ifndef CONFIG_DRIVER_TI_EMAC
#endif

#ifdef CONFIG_USE_NAND
#define CONFIG_CMD_NAND

#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
#define CONFIG_CMD_UBIFS
#endif

#if !defined(CONFIG_USE_NAND) && \
	!defined(CONFIG_SYS_USE_NOR) && \
	!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE		(16 << 10)
#undef CONFIG_CMD_ENV
#endif

/* SD/MMC */
#ifdef CONFIG_MMC
#undef CONFIG_ENV_IS_IN_MMC
#endif

#ifdef CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_SIZE
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NAND
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#endif

#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_TEXT_BASE	0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT	32768
#define CONFIG_SPL_PAD_TO	32768
#endif

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
					GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
Commit	Line	Data
a868e443 PH	1	/*
	2	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* Based on davinci_dvevm.h. Original Copyrights follow:
	5	*
	6	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	7	*
5b8031cc	8	* SPDX-License-Identifier: GPL-2.0
a868e443 PH	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* Board
	16	*/
	17	#define CONFIG_DRIVER_TI_EMAC
	18	#undef CONFIG_USE_SPIFLASH
	19	#undef CONFIG_SYS_USE_NOR
	20	#define CONFIG_USE_NAND
	21
	22	/*
	23	* SoC Configuration
	24	*/
	25	#define CONFIG_MACH_OMAPL138_LCDK
	26	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
	27	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
	28	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	29	#define CONFIG_SYS_OSCIN_FREQ 24000000
	30	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	31	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
	32	#define CONFIG_SYS_HZ 1000
	33	#define CONFIG_SKIP_LOWLEVEL_INIT
	34	#define CONFIG_SYS_TEXT_BASE 0xc1080000
	35
	36	/*
	37	* Memory Info
	38	*/
	39	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
	40	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
	41	#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
	42	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
	43
	44	/* memtest start addr */
	45	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
	46
	47	/* memtest will be run on 16MB */
	48	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 1610241024)
	49
	50	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	51	#define CONFIG_STACKSIZE (2561024) / regular stack */
	52
	53	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	54	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	55	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	56	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	57	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	58	DAVINCI_SYSCFG_SUSPSRC_I2C)
	59
	60	/*
	61	* PLL configuration
	62	*/
	63	#define CONFIG_SYS_DV_CLKMODE 0
	64	#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
	65	#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
	66	#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
	67	#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
	68	#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
	69	#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
	70	#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
	71	#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
	72
73	#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
74	#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
75	#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
76	#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
77
1601dd97	78	#define CONFIG_SYS_DA850_PLL0_PLLM 37
a868e443 PH	79	#define CONFIG_SYS_DA850_PLL1_PLLM 21
a868e443 PH	80
a5ab44f6 FP	81	/*
	82	* DDR2 memory configuration
	83	*/
	84	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	85	DV_DDR_PHY_EXT_STRBEN \| \
	86	(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	87
	88	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	89	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) \| \
	90	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	91	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	92	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	93	(4 << DV_DDR_SDCR_CL_SHIFT) \| \
	94	(3 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	95	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	96
	97	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	98	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	99
	100	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	101	(19 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	102	(1 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	103	(1 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	104	(2 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	105	(6 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	106	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	107	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	108	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
	109
	110	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	111	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	112	(2 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	113	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	114	(10 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	115	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	116	(1 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	117	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
	118
	119	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
	120	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
	121
a868e443 PH	122	/*
	123	* Serial Driver info
	124	*/
a868e443 PH	125	#define CONFIG_SYS_NS16550_SERIAL
	126	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
	127	#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
	128	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
	129	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
	130	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
	131	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	132
	133	#define CONFIG_SPI
a868e443 PH	134	#define CONFIG_DAVINCI_SPI
	135	#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
	136	#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
	137	#define CONFIG_SF_DEFAULT_SPEED 30000000
	138	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	139
	140	#ifdef CONFIG_USE_SPIFLASH
a868e443 PH	141	#define CONFIG_SPL_SPI_LOAD
	142	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
	143	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
	144	#endif
	145
	146	/*
	147	* I2C Configuration
	148	*/
	149	#define CONFIG_SYS_I2C
	150	#define CONFIG_SYS_I2C_DAVINCI
	151	#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
	152	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
	153	#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
	154
	155	/*
	156	* Flash & Environment
	157	*/
	158	#ifdef CONFIG_USE_NAND
	159	#undef CONFIG_ENV_IS_IN_FLASH
	160	#define CONFIG_NAND_DAVINCI
a868e443 PH	161	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
	162	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
	163	#define CONFIG_ENV_SIZE (128 << 9)
	164	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	165	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	166	#define CONFIG_SYS_NAND_PAGE_2K
d92ca46e	167	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
a868e443 PH	168	#define CONFIG_SYS_NAND_CS 3
a868e443 PH	169	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
1dbab274	170	#define CONFIG_SYS_NAND_MASK_CLE 0x10
ef044796	171	#define CONFIG_SYS_NAND_MASK_ALE 0x8
a868e443 PH	172	#undef CONFIG_SYS_NAND_HW_ECC
a868e443 PH	173	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
c69a05d0	174	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
2b2cab24	175	#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
c69a05d0 FP	176	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	177	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	178	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
c0c10449	179	#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
c69a05d0 FP	180	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	181	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	182	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	183	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	184	CONFIG_SYS_MALLOC_LEN - \
	185	GENERATED_GBL_DATA_SIZE)
	186	#define CONFIG_SYS_NAND_ECCPOS { \
2b2cab24 FP	187	6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
	188	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
	189	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
	190	54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
c69a05d0 FP	191	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	192	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	193	#define CONFIG_SYS_NAND_ECCSIZE 512
	194	#define CONFIG_SYS_NAND_ECCBYTES 10
	195	#define CONFIG_SYS_NAND_OOBSIZE 64
	196	#define CONFIG_SPL_NAND_BASE
	197	#define CONFIG_SPL_NAND_DRIVERS
	198	#define CONFIG_SPL_NAND_ECC
	199	#define CONFIG_SPL_NAND_SIMPLE
	200	#define CONFIG_SPL_NAND_LOAD
a868e443 PH	201	#endif
	202
	203	#ifdef CONFIG_SYS_USE_NOR
	204	#define CONFIG_ENV_IS_IN_FLASH
a868e443 PH	205	#define CONFIG_FLASH_CFI_DRIVER
	206	#define CONFIG_SYS_FLASH_CFI
	207	#define CONFIG_SYS_FLASH_PROTECTION
	208	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	209	#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
	210	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
	211	#define CONFIG_ENV_SIZE (128 << 10)
	212	#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
	213	#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
	214	#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	215	+ 3)
	216	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
	217	#endif
	218
	219	#ifdef CONFIG_USE_SPIFLASH
	220	#undef CONFIG_ENV_IS_IN_FLASH
	221	#undef CONFIG_ENV_IS_IN_NAND
	222	#define CONFIG_ENV_IS_IN_SPI_FLASH
	223	#define CONFIG_ENV_SIZE (64 << 10)
	224	#define CONFIG_ENV_OFFSET (256 << 10)
	225	#define CONFIG_ENV_SECT_SIZE (64 << 10)
a868e443 PH	226	#endif
	227
	228	/*
	229	* Network & Ethernet Configuration
	230	*/
	231	#ifdef CONFIG_DRIVER_TI_EMAC
	232	#define CONFIG_EMAC_MDIO_PHY_NUM 7
	233	#define CONFIG_MII
	234	#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
	235	#define CONFIG_BOOTP_DEFAULT
	236	#define CONFIG_BOOTP_DNS
	237	#define CONFIG_BOOTP_DNS2
	238	#define CONFIG_BOOTP_SEND_HOSTNAME
	239	#define CONFIG_NET_RETRY_COUNT 10
a868e443 PH	240	#endif
	241
	242	/*
	243	* U-Boot general configuration
	244	*/
a868e443	245	#define CONFIG_MISC_INIT_R
963ed6f3	246	#define CONFIG_BOOTFILE "zImage" /* Boot file name */
a868e443 PH	247	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	248	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	249	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	250	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
	251	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
a868e443	252	#define CONFIG_AUTO_COMPLETE
a868e443 PH	253	#define CONFIG_CMDLINE_EDITING
	254	#define CONFIG_SYS_LONGHELP
	255	#define CONFIG_CRC32_VERIFY
	256	#define CONFIG_MX_CYCLIC
a868e443 PH	257
	258	/*
	259	* Linux Information
	260	*/
	261	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
	262	#define CONFIG_CMDLINE_TAG
	263	#define CONFIG_REVISION_TAG
	264	#define CONFIG_SETUP_MEMORY_TAGS
	265	#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
f96ab6a4 FP	266	#define CONFIG_BOOTCOMMAND \
	267	"if mmc rescan; then " \
	268	"run mmcboot; " \
	269	"else " \
	270	"run spiboot; " \
	271	"fi"
	272	#define CONFIG_EXTRA_ENV_SETTINGS \
5ca28f67 FP	273	"fdtaddr=0xc0600000\0" \
5ca28f67 FP	274	"fdtfile=da850-lcdk.dtb\0" \
963ed6f3	275	"fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \
f96ab6a4 FP	276	"mmcboot=" \
	277	"if fatload mmc 0 0xc0600000 boot.scr; then " \
	278	"source 0xc0600000; " \
	279	"else " \
963ed6f3 FP	280	"fatload mmc 0 0xc0700000 " \
963ed6f3 FP	281	__stringify(CONFIG_BOOTFILE) "; " \
5ca28f67 FP	282	"fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
5ca28f67 FP	283	"run fdtboot; " \
f96ab6a4 FP	284	"fi;\0" \
	285	"spiboot=" \
	286	"sf probe 0; " \
	287	"sf read 0xc0700000 0x80000 0x220000; " \
963ed6f3	288	"bootz 0xc0700000;\0"
a868e443 PH	289
	290	/*
	291	* U-Boot commands
	292	*/
a868e443	293	#define CONFIG_CMD_ENV
a868e443	294	#define CONFIG_CMD_DIAG
a868e443	295	#define CONFIG_CMD_SAVES
a868e443 PH	296	#ifdef CONFIG_CMD_BDI
	297	#define CONFIG_CLOCKS
	298	#endif
	299
	300	#ifndef CONFIG_DRIVER_TI_EMAC
a868e443 PH	301	#endif
	302
	303	#ifdef CONFIG_USE_NAND
a868e443 PH	304	#define CONFIG_CMD_NAND
	305
	306	#define CONFIG_CMD_MTDPARTS
	307	#define CONFIG_MTD_DEVICE
	308	#define CONFIG_MTD_PARTITIONS
	309	#define CONFIG_LZO
	310	#define CONFIG_RBTREE
a868e443 PH	311	#define CONFIG_CMD_UBIFS
	312	#endif
	313
a868e443 PH	314	#if !defined(CONFIG_USE_NAND) && \
	315	!defined(CONFIG_SYS_USE_NOR) && \
	316	!defined(CONFIG_USE_SPIFLASH)
	317	#define CONFIG_ENV_IS_NOWHERE
a868e443	318	#define CONFIG_ENV_SIZE (16 << 10)
a868e443 PH	319	#undef CONFIG_CMD_ENV
	320	#endif
	321
	322	/* SD/MMC */
a868e443	323	#ifdef CONFIG_MMC
a868e443 PH	324	#undef CONFIG_ENV_IS_IN_MMC
	325	#endif
	326
	327	#ifdef CONFIG_ENV_IS_IN_MMC
	328	#undef CONFIG_ENV_SIZE
	329	#undef CONFIG_ENV_OFFSET
	330	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
	331	#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
	332	#undef CONFIG_ENV_IS_IN_FLASH
	333	#undef CONFIG_ENV_IS_IN_NAND
	334	#undef CONFIG_ENV_IS_IN_SPI_FLASH
	335	#endif
	336
	337	#ifndef CONFIG_DIRECT_NOR_BOOT
	338	/* defines for SPL */
	339	#define CONFIG_SPL_FRAMEWORK
	340	#define CONFIG_SPL_BOARD_INIT
	341	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	342	CONFIG_SYS_MALLOC_LEN)
	343	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
a868e443 PH	344	#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
	345	#define CONFIG_SPL_STACK 0x8001ff00
	346	#define CONFIG_SPL_TEXT_BASE 0x80000000
	347	#define CONFIG_SPL_MAX_FOOTPRINT 32768
	348	#define CONFIG_SPL_PAD_TO 32768
	349	#endif
	350
	351	/* additions for new relocation code, must added to all boards */
	352	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
	353	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
	354	GENERATED_GBL_DATA_SIZE)
	355	#endif /* __CONFIG_H */