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[people/ms/u-boot.git] / include / configs / ot1200.h
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1/*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 Bachmann electronic GmbH
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include "mx6_common.h"
39d09733 12
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13/* Size of malloc() pool */
14#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
15
39d09733 16#define CONFIG_MISC_INIT_R
39d09733 17
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18/* UART Configs */
19#define CONFIG_MXC_UART
20#define CONFIG_MXC_UART_BASE UART1_BASE
21
22/* SF Configs */
39d09733 23#define CONFIG_SPI
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24#define CONFIG_MXC_SPI
25#define CONFIG_SF_DEFAULT_BUS 2
2e3a1f4d 26#define CONFIG_SF_DEFAULT_CS 0
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27#define CONFIG_SF_DEFAULT_SPEED 25000000
28#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
29
30/* IO expander */
31#define CONFIG_PCA953X
32#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
33#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
34#define CONFIG_CMD_PCA953X
35#define CONFIG_CMD_PCA953X_INFO
36
37/* I2C Configs */
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38#define CONFIG_SYS_I2C
39#define CONFIG_SYS_I2C_MXC
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40#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
41#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 42#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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43#define CONFIG_SYS_I2C_SPEED 100000
44
45/* OCOTP Configs */
46#define CONFIG_CMD_IMXOTP
47#define CONFIG_IMX_OTP
48#define IMX_OTP_BASE OCOTP_BASE_ADDR
49#define IMX_OTP_ADDR_MAX 0x7F
50#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
51#define IMX_OTPWRITE_ENABLED
52
53/* MMC Configs */
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54#define CONFIG_SYS_FSL_ESDHC_ADDR 0
55#define CONFIG_SYS_FSL_USDHC_NUM 2
56
39c7d5a2 57/* USB Configs */
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58#define CONFIG_USB_EHCI
59#define CONFIG_USB_EHCI_MX6
60#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
61#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
62
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63#ifdef CONFIG_MX6Q
64#define CONFIG_CMD_SATA
65#endif
66
67/*
68 * SATA Configs
69 */
70#ifdef CONFIG_CMD_SATA
71#define CONFIG_DWC_AHSATA
72#define CONFIG_SYS_SATA_MAX_DEVICE 1
73#define CONFIG_DWC_AHSATA_PORT_ID 0
74#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
75#define CONFIG_LBA48
76#define CONFIG_LIBATA
77#endif
78
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79/* SPL */
80#ifdef CONFIG_SPL
81#include "imx6_spl.h"
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82#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
83#define CONFIG_SPL_SPI_LOAD
84#endif
85
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86#define CONFIG_FEC_MXC
87#define CONFIG_MII
88#define IMX_FEC_BASE ENET_BASE_ADDR
89#define CONFIG_FEC_XCV_TYPE MII100
90#define CONFIG_ETHPRIME "FEC"
91#define CONFIG_FEC_MXC_PHYADDR 0x5
92#define CONFIG_PHYLIB
93#define CONFIG_PHY_SMSC
94
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95#ifndef CONFIG_SPL
96#define CONFIG_CMD_EEPROM
97#define CONFIG_ENV_EEPROM_IS_ON_I2C
98#define CONFIG_SYS_I2C_EEPROM_BUS 1
99#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
100#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
101#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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102#endif
103
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104/* Miscellaneous commands */
105#define CONFIG_CMD_BMODE
39d09733 106
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107#define CONFIG_PREBOOT ""
108
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109/* Print Buffer Size */
110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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111
112/* Physical Memory Map */
113#define CONFIG_NR_DRAM_BANKS 1
114#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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115
116#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
117#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
118#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
119
120#define CONFIG_SYS_INIT_SP_OFFSET \
121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
122#define CONFIG_SYS_INIT_SP_ADDR \
123 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
124
056845c2 125/* Environment organization */
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126#define CONFIG_ENV_IS_IN_SPI_FLASH
127#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
128#define CONFIG_ENV_OFFSET (1024 * 1024)
129/* M25P16 has an erase size of 64 KiB */
130#define CONFIG_ENV_SECT_SIZE (64 * 1024)
131#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
132#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
133#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
134#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
135
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136#define CONFIG_BOOTP_SERVERIP
137#define CONFIG_BOOTP_BOOTFILE
138
139#endif /* __CONFIG_H */