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14aa71e6 LY |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
14aa71e6 LY |
5 | */ |
6 | ||
7 | /* | |
8 | * QorIQ RDB boards configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #ifdef CONFIG_36BIT | |
14 | #define CONFIG_PHYS_64BIT | |
15 | #endif | |
16 | ||
17 | #if defined(CONFIG_P1020MBG) | |
e2c91b95 | 18 | #define CONFIG_BOARDNAME "P1020MBG-PC" |
14aa71e6 LY |
19 | #define CONFIG_P1020 |
20 | #define CONFIG_VSC7385_ENET | |
21 | #define CONFIG_SLIC | |
22 | #define __SW_BOOT_MASK 0x03 | |
23 | #define __SW_BOOT_NOR 0xe4 | |
24 | #define __SW_BOOT_SD 0x54 | |
13d1143f | 25 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
26 | #endif |
27 | ||
28 | #if defined(CONFIG_P1020UTM) | |
e2c91b95 | 29 | #define CONFIG_BOARDNAME "P1020UTM-PC" |
14aa71e6 LY |
30 | #define CONFIG_P1020 |
31 | #define __SW_BOOT_MASK 0x03 | |
32 | #define __SW_BOOT_NOR 0xe0 | |
33 | #define __SW_BOOT_SD 0x50 | |
13d1143f | 34 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
35 | #endif |
36 | ||
37 | #if defined(CONFIG_P1020RDB) | |
e2c91b95 | 38 | #define CONFIG_BOARDNAME "P1020RDB-PC" |
14aa71e6 LY |
39 | #define CONFIG_NAND_FSL_ELBC |
40 | #define CONFIG_P1020 | |
41 | #define CONFIG_SPI_FLASH | |
42 | #define CONFIG_VSC7385_ENET | |
43 | #define CONFIG_SLIC | |
44 | #define __SW_BOOT_MASK 0x03 | |
45 | #define __SW_BOOT_NOR 0x5c | |
46 | #define __SW_BOOT_SPI 0x1c | |
47 | #define __SW_BOOT_SD 0x9c | |
48 | #define __SW_BOOT_NAND 0xec | |
49 | #define __SW_BOOT_PCIE 0x6c | |
13d1143f | 50 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
51 | #endif |
52 | ||
53 | #if defined(CONFIG_P1021RDB) | |
e2c91b95 | 54 | #define CONFIG_BOARDNAME "P1021RDB-PC" |
14aa71e6 LY |
55 | #define CONFIG_NAND_FSL_ELBC |
56 | #define CONFIG_P1021 | |
57 | #define CONFIG_QE | |
58 | #define CONFIG_SPI_FLASH | |
59 | #define CONFIG_VSC7385_ENET | |
60 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
61 | addresses in the LBC */ | |
62 | #define __SW_BOOT_MASK 0x03 | |
63 | #define __SW_BOOT_NOR 0x5c | |
64 | #define __SW_BOOT_SPI 0x1c | |
65 | #define __SW_BOOT_SD 0x9c | |
66 | #define __SW_BOOT_NAND 0xec | |
67 | #define __SW_BOOT_PCIE 0x6c | |
13d1143f | 68 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
69 | #endif |
70 | ||
71 | #if defined(CONFIG_P1024RDB) | |
72 | #define CONFIG_BOARDNAME "P1024RDB" | |
73 | #define CONFIG_NAND_FSL_ELBC | |
74 | #define CONFIG_P1024 | |
75 | #define CONFIG_SLIC | |
76 | #define CONFIG_SPI_FLASH | |
77 | #define __SW_BOOT_MASK 0xf3 | |
78 | #define __SW_BOOT_NOR 0x00 | |
79 | #define __SW_BOOT_SPI 0x08 | |
80 | #define __SW_BOOT_SD 0x04 | |
81 | #define __SW_BOOT_NAND 0x0c | |
13d1143f | 82 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
83 | #endif |
84 | ||
85 | #if defined(CONFIG_P1025RDB) | |
86 | #define CONFIG_BOARDNAME "P1025RDB" | |
87 | #define CONFIG_NAND_FSL_ELBC | |
88 | #define CONFIG_P1025 | |
89 | #define CONFIG_QE | |
90 | #define CONFIG_SLIC | |
91 | #define CONFIG_SPI_FLASH | |
92 | ||
93 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
94 | addresses in the LBC */ | |
95 | #define __SW_BOOT_MASK 0xf3 | |
96 | #define __SW_BOOT_NOR 0x00 | |
97 | #define __SW_BOOT_SPI 0x08 | |
98 | #define __SW_BOOT_SD 0x04 | |
99 | #define __SW_BOOT_NAND 0x0c | |
13d1143f | 100 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
101 | #endif |
102 | ||
103 | #if defined(CONFIG_P2020RDB) | |
e2c91b95 | 104 | #define CONFIG_BOARDNAME "P2020RDB-PCA" |
14aa71e6 LY |
105 | #define CONFIG_NAND_FSL_ELBC |
106 | #define CONFIG_P2020 | |
107 | #define CONFIG_SPI_FLASH | |
108 | #define CONFIG_VSC7385_ENET | |
109 | #define __SW_BOOT_MASK 0x03 | |
110 | #define __SW_BOOT_NOR 0xc8 | |
111 | #define __SW_BOOT_SPI 0x28 | |
112 | #define __SW_BOOT_SD 0x68 /* or 0x18 */ | |
113 | #define __SW_BOOT_NAND 0xe8 | |
114 | #define __SW_BOOT_PCIE 0xa8 | |
13d1143f SW |
115 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
116 | #endif | |
117 | ||
118 | #if CONFIG_SYS_L2_SIZE >= (512 << 10) | |
119 | /* must be 32-bit */ | |
120 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
121 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
122 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
14aa71e6 LY |
123 | #endif |
124 | ||
125 | #ifdef CONFIG_SDCARD | |
126 | #define CONFIG_RAMBOOT_SDCARD | |
127 | #define CONFIG_SYS_RAMBOOT | |
128 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
129 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
130 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
131 | #endif | |
132 | ||
133 | #ifdef CONFIG_SPIFLASH | |
134 | #define CONFIG_RAMBOOT_SPIFLASH | |
135 | #define CONFIG_SYS_RAMBOOT | |
136 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
137 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
138 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
139 | #endif | |
140 | ||
a796e72c SW |
141 | #ifdef CONFIG_NAND |
142 | #define CONFIG_SPL | |
143 | #define CONFIG_SPL_INIT_MINIMAL | |
144 | #define CONFIG_SPL_SERIAL_SUPPORT | |
145 | #define CONFIG_SPL_NAND_SUPPORT | |
146 | #define CONFIG_SPL_NAND_MINIMAL | |
147 | #define CONFIG_SPL_FLUSH_IMAGE | |
148 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
149 | ||
a796e72c | 150 | #define CONFIG_SPL_TEXT_BASE 0xfffff000 |
6113d3f2 | 151 | #define CONFIG_SPL_MAX_SIZE 4096 |
13d1143f SW |
152 | |
153 | #ifdef CONFIG_SYS_INIT_L2_ADDR | |
154 | /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ | |
155 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 | |
156 | #define CONFIG_SPL_RELOC_TEXT_BASE \ | |
157 | (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) | |
158 | #define CONFIG_SPL_RELOC_STACK \ | |
159 | (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) | |
160 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
161 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
162 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) | |
163 | #else | |
164 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
a796e72c SW |
165 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 |
166 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
a796e72c SW |
167 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
168 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
13d1143f SW |
169 | #endif |
170 | ||
171 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
a796e72c SW |
172 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 |
173 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
14aa71e6 LY |
174 | #endif |
175 | ||
176 | #ifndef CONFIG_SYS_TEXT_BASE | |
177 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
178 | #endif | |
179 | ||
180 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
181 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
182 | #endif | |
183 | ||
184 | #ifndef CONFIG_SYS_MONITOR_BASE | |
a796e72c SW |
185 | #ifdef CONFIG_SPL_BUILD |
186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
187 | #else | |
14aa71e6 LY |
188 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
189 | #endif | |
a796e72c | 190 | #endif |
14aa71e6 LY |
191 | |
192 | /* High Level Configuration Options */ | |
193 | #define CONFIG_BOOKE | |
194 | #define CONFIG_E500 | |
195 | #define CONFIG_MPC85xx | |
196 | ||
197 | #define CONFIG_MP | |
198 | ||
199 | #define CONFIG_FSL_ELBC | |
200 | #define CONFIG_PCI | |
201 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
202 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
203 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
842033e6 | 204 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
14aa71e6 LY |
205 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
206 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
207 | ||
208 | #define CONFIG_FSL_LAW | |
209 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
210 | #define CONFIG_ENV_OVERWRITE | |
211 | ||
212 | #define CONFIG_CMD_SATA | |
befb7d9f | 213 | #define CONFIG_SATA_SIL |
14aa71e6 LY |
214 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
215 | #define CONFIG_LIBATA | |
216 | #define CONFIG_LBA48 | |
217 | ||
218 | #if defined(CONFIG_P2020RDB) | |
219 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
220 | #else | |
221 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
222 | #endif | |
223 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
224 | ||
225 | #define CONFIG_HWCONFIG | |
226 | /* | |
227 | * These can be toggled for performance analysis, otherwise use default. | |
228 | */ | |
229 | #define CONFIG_L2_CACHE | |
230 | #define CONFIG_BTB | |
231 | ||
232 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
babb348c | 233 | |
14aa71e6 | 234 | #define CONFIG_ENABLE_36BIT_PHYS |
14aa71e6 LY |
235 | |
236 | #ifdef CONFIG_PHYS_64BIT | |
237 | #define CONFIG_ADDR_MAP 1 | |
238 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
239 | #endif | |
240 | ||
241 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
242 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
243 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
244 | ||
245 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
246 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
247 | ||
248 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k | |
249 | SPL code*/ | |
a796e72c | 250 | #ifdef CONFIG_SPL_BUILD |
14aa71e6 LY |
251 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
252 | #endif | |
253 | ||
254 | /* DDR Setup */ | |
255 | #define CONFIG_FSL_DDR3 | |
1ba62f10 | 256 | #define CONFIG_SYS_DDR_RAW_TIMING |
14aa71e6 LY |
257 | #define CONFIG_DDR_SPD |
258 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
259 | #define SPD_EEPROM_ADDRESS 0x52 | |
6f5e1dc5 | 260 | #undef CONFIG_FSL_DDR_INTERACTIVE |
14aa71e6 LY |
261 | |
262 | #ifdef CONFIG_P1020MBG | |
263 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G | |
264 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
265 | #else | |
266 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G | |
267 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
268 | #endif | |
269 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) | |
270 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
271 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
272 | ||
273 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
274 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
275 | ||
276 | /* Default settings for DDR3 */ | |
13d1143f | 277 | #ifndef CONFIG_P2020RDB |
14aa71e6 LY |
278 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
279 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
280 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
281 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f | |
282 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 | |
283 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 | |
284 | ||
285 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
286 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
287 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
288 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
289 | ||
290 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
291 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 | |
292 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
293 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
294 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
295 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ | |
296 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 | |
297 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
298 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
299 | ||
300 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
301 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
302 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 | |
303 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF | |
304 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
305 | #define CONFIG_SYS_DDR_MODE_1 0x40461520 | |
306 | #define CONFIG_SYS_DDR_MODE_2 0x8000c000 | |
307 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 | |
308 | #endif | |
309 | ||
310 | #undef CONFIG_CLOCKS_IN_MHZ | |
311 | ||
312 | /* | |
313 | * Memory map | |
314 | * | |
d674bccf | 315 | * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable |
14aa71e6 | 316 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) |
d674bccf | 317 | * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 |
13d1143f SW |
318 | * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable |
319 | * (early boot only) | |
d674bccf SW |
320 | * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 |
321 | * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 | |
322 | * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 | |
323 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 | |
14aa71e6 | 324 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
d674bccf | 325 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable |
d674bccf | 326 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
14aa71e6 LY |
327 | */ |
328 | ||
329 | ||
330 | /* | |
331 | * Local Bus Definitions | |
332 | */ | |
333 | #if defined(CONFIG_P1020MBG) | |
334 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ | |
335 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
336 | #elif defined(CONFIG_P1020UTM) | |
337 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
338 | #define CONFIG_SYS_FLASH_BASE 0xee000000 | |
339 | #else | |
340 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ | |
341 | #define CONFIG_SYS_FLASH_BASE 0xef000000 | |
342 | #endif | |
343 | ||
344 | ||
345 | #ifdef CONFIG_PHYS_64BIT | |
346 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
347 | #else | |
348 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
349 | #endif | |
350 | ||
7ee41107 | 351 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
14aa71e6 LY |
352 | | BR_PS_16 | BR_V) |
353 | ||
354 | #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 | |
355 | ||
356 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
357 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
358 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
359 | ||
360 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
361 | ||
362 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
363 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
364 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
365 | ||
366 | #define CONFIG_FLASH_CFI_DRIVER | |
367 | #define CONFIG_SYS_FLASH_CFI | |
368 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
369 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
370 | ||
371 | /* Nand Flash */ | |
372 | #ifdef CONFIG_NAND_FSL_ELBC | |
373 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
374 | #ifdef CONFIG_PHYS_64BIT | |
375 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
376 | #else | |
377 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
378 | #endif | |
379 | ||
380 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
381 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
382 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
383 | #define CONFIG_CMD_NAND | |
384 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
385 | ||
7ee41107 | 386 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
14aa71e6 LY |
387 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
388 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
389 | | BR_MS_FCM /* MSEL = FCM */ \ | |
390 | | BR_V) /* valid */ | |
391 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ | |
392 | | OR_FCM_CSCT \ | |
393 | | OR_FCM_CST \ | |
394 | | OR_FCM_CHT \ | |
395 | | OR_FCM_SCY_1 \ | |
396 | | OR_FCM_TRLX \ | |
397 | | OR_FCM_EHTR) | |
398 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
399 | ||
400 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
401 | ||
402 | #define CONFIG_SYS_INIT_RAM_LOCK | |
403 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
404 | #ifdef CONFIG_PHYS_64BIT | |
405 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
406 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
407 | /* The assembler doesn't like typecast */ | |
408 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
409 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
410 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
411 | #else | |
412 | /* Initial L1 address */ | |
413 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
414 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
415 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
416 | #endif | |
417 | /* Size of used area in RAM */ | |
418 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
419 | ||
420 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
421 | GENERATED_GBL_DATA_SIZE) | |
422 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
423 | ||
424 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ | |
425 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ | |
426 | ||
427 | #define CONFIG_SYS_CPLD_BASE 0xffa00000 | |
428 | #ifdef CONFIG_PHYS_64BIT | |
429 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull | |
430 | #else | |
431 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
432 | #endif | |
433 | /* CPLD config size: 1Mb */ | |
434 | #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ | |
435 | BR_PS_8 | BR_V) | |
436 | #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) | |
437 | ||
438 | #define CONFIG_SYS_PMC_BASE 0xff980000 | |
439 | #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE | |
440 | #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ | |
441 | BR_PS_8 | BR_V) | |
442 | #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
443 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ | |
444 | OR_GPCM_EAD) | |
445 | ||
a796e72c | 446 | #ifdef CONFIG_NAND |
14aa71e6 LY |
447 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ |
448 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
449 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
450 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
451 | #else | |
452 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
453 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
454 | #ifdef CONFIG_NAND_FSL_ELBC | |
455 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ | |
456 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
457 | #endif | |
458 | #endif | |
459 | #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ | |
460 | #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ | |
461 | ||
462 | ||
463 | /* Vsc7385 switch */ | |
464 | #ifdef CONFIG_VSC7385_ENET | |
465 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
466 | ||
467 | #ifdef CONFIG_PHYS_64BIT | |
468 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
469 | #else | |
470 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE | |
471 | #endif | |
472 | ||
473 | #define CONFIG_SYS_VSC7385_BR_PRELIM \ | |
474 | (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) | |
475 | #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ | |
476 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ | |
477 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
478 | ||
479 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM | |
480 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM | |
481 | ||
482 | /* The size of the VSC7385 firmware image */ | |
483 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
484 | #endif | |
485 | ||
486 | /* Serial Port - controlled on board with jumper J8 | |
487 | * open - index 2 | |
488 | * shorted - index 1 | |
489 | */ | |
490 | #define CONFIG_CONS_INDEX 1 | |
491 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
492 | #define CONFIG_SYS_NS16550 | |
493 | #define CONFIG_SYS_NS16550_SERIAL | |
494 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
495 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
a796e72c | 496 | #ifdef CONFIG_SPL_BUILD |
14aa71e6 LY |
497 | #define CONFIG_NS16550_MIN_FUNCTIONS |
498 | #endif | |
499 | ||
500 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
501 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
502 | ||
503 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
504 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
505 | ||
506 | /* Use the HUSH parser */ | |
507 | #define CONFIG_SYS_HUSH_PARSER | |
14aa71e6 LY |
508 | |
509 | /* | |
510 | * Pass open firmware flat tree | |
511 | */ | |
512 | #define CONFIG_OF_LIBFDT | |
513 | #define CONFIG_OF_BOARD_SETUP | |
514 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
515 | ||
14aa71e6 LY |
516 | /* new uImage format support */ |
517 | #define CONFIG_FIT | |
518 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
519 | ||
520 | /* I2C */ | |
521 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
522 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
523 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
524 | #define CONFIG_I2C_MULTI_BUS | |
525 | #define CONFIG_I2C_CMD_TREE | |
526 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ | |
527 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
528 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
529 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ | |
530 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
531 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
532 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ | |
533 | ||
534 | /* | |
535 | * I2C2 EEPROM | |
536 | */ | |
537 | #undef CONFIG_ID_EEPROM | |
538 | ||
539 | #define CONFIG_RTC_PT7C4338 | |
540 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
541 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 | |
542 | ||
543 | /* enable read and write access to EEPROM */ | |
544 | #define CONFIG_CMD_EEPROM | |
545 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
546 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
547 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
548 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
549 | ||
550 | /* | |
551 | * eSPI - Enhanced SPI | |
552 | */ | |
553 | #define CONFIG_HARD_SPI | |
554 | #define CONFIG_FSL_ESPI | |
555 | ||
556 | #if defined(CONFIG_SPI_FLASH) | |
557 | #define CONFIG_SPI_FLASH_SPANSION | |
558 | #define CONFIG_CMD_SF | |
559 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
560 | #define CONFIG_SF_DEFAULT_MODE 0 | |
561 | #endif | |
562 | ||
563 | #if defined(CONFIG_PCI) | |
564 | /* | |
565 | * General PCI | |
566 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
567 | */ | |
568 | ||
569 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
570 | #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" | |
571 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
572 | #ifdef CONFIG_PHYS_64BIT | |
573 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
574 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
575 | #else | |
576 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
577 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
578 | #endif | |
579 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
580 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
581 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
582 | #ifdef CONFIG_PHYS_64BIT | |
583 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
584 | #else | |
585 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
586 | #endif | |
587 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
588 | ||
589 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
590 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" | |
591 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
592 | #ifdef CONFIG_PHYS_64BIT | |
593 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
594 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
595 | #else | |
596 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
597 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
598 | #endif | |
599 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
600 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
601 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
602 | #ifdef CONFIG_PHYS_64BIT | |
603 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
604 | #else | |
605 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
606 | #endif | |
607 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
608 | ||
14aa71e6 LY |
609 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
610 | #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ | |
611 | #define CONFIG_CMD_PCI | |
612 | #define CONFIG_CMD_NET | |
613 | ||
614 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
615 | #define CONFIG_DOS_PARTITION | |
616 | #endif /* CONFIG_PCI */ | |
617 | ||
618 | #if defined(CONFIG_TSEC_ENET) | |
14aa71e6 LY |
619 | #define CONFIG_MII /* MII PHY management */ |
620 | #define CONFIG_TSEC1 | |
621 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
622 | #define CONFIG_TSEC2 | |
623 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
624 | #define CONFIG_TSEC3 | |
625 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
626 | ||
627 | #define TSEC1_PHY_ADDR 2 | |
628 | #define TSEC2_PHY_ADDR 0 | |
629 | #define TSEC3_PHY_ADDR 1 | |
630 | ||
631 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
632 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
633 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
634 | ||
635 | #define TSEC1_PHYIDX 0 | |
636 | #define TSEC2_PHYIDX 0 | |
637 | #define TSEC3_PHYIDX 0 | |
638 | ||
639 | #define CONFIG_ETHPRIME "eTSEC1" | |
640 | ||
641 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
642 | ||
643 | #define CONFIG_HAS_ETH0 | |
644 | #define CONFIG_HAS_ETH1 | |
645 | #define CONFIG_HAS_ETH2 | |
646 | #endif /* CONFIG_TSEC_ENET */ | |
647 | ||
648 | #ifdef CONFIG_QE | |
649 | /* QE microcode/firmware address */ | |
f2717b47 TT |
650 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
651 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 | |
652 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
14aa71e6 LY |
653 | #endif /* CONFIG_QE */ |
654 | ||
655 | #ifdef CONFIG_P1025RDB | |
656 | /* | |
657 | * QE UEC ethernet configuration | |
658 | */ | |
659 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
660 | ||
661 | #undef CONFIG_UEC_ETH | |
662 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
663 | ||
664 | #define CONFIG_UEC_ETH1 /* ETH1 */ | |
665 | #define CONFIG_HAS_ETH0 | |
666 | ||
667 | #ifdef CONFIG_UEC_ETH1 | |
668 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
669 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ | |
670 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ | |
671 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
672 | #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ | |
673 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
674 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 | |
675 | #endif /* CONFIG_UEC_ETH1 */ | |
676 | ||
677 | #define CONFIG_UEC_ETH5 /* ETH5 */ | |
678 | #define CONFIG_HAS_ETH1 | |
679 | ||
680 | #ifdef CONFIG_UEC_ETH5 | |
681 | #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ | |
682 | #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE | |
683 | #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ | |
684 | #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH | |
685 | #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ | |
686 | #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
687 | #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 | |
688 | #endif /* CONFIG_UEC_ETH5 */ | |
689 | #endif /* CONFIG_P1025RDB */ | |
690 | ||
691 | /* | |
692 | * Environment | |
693 | */ | |
14aa71e6 LY |
694 | #ifdef CONFIG_RAMBOOT_SPIFLASH |
695 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
696 | #define CONFIG_ENV_SPI_BUS 0 | |
697 | #define CONFIG_ENV_SPI_CS 0 | |
698 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
699 | #define CONFIG_ENV_SPI_MODE 0 | |
700 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
701 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
702 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
703 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
704 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 705 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
14aa71e6 LY |
706 | #define CONFIG_ENV_SIZE 0x2000 |
707 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
a796e72c | 708 | #elif defined(CONFIG_NAND) |
14aa71e6 LY |
709 | #define CONFIG_ENV_IS_IN_NAND |
710 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
711 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
712 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) | |
a796e72c | 713 | #elif defined(CONFIG_SYS_RAMBOOT) |
14aa71e6 LY |
714 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
715 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
716 | #define CONFIG_ENV_SIZE 0x2000 | |
14aa71e6 LY |
717 | #else |
718 | #define CONFIG_ENV_IS_IN_FLASH | |
719 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
720 | #define CONFIG_ENV_ADDR 0xfff80000 | |
721 | #else | |
722 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
723 | #endif | |
724 | #define CONFIG_ENV_SIZE 0x2000 | |
725 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
726 | #endif | |
727 | ||
728 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
729 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
730 | ||
731 | /* | |
732 | * Command line configuration. | |
733 | */ | |
734 | #include <config_cmd_default.h> | |
735 | ||
736 | #define CONFIG_CMD_IRQ | |
737 | #define CONFIG_CMD_PING | |
738 | #define CONFIG_CMD_I2C | |
739 | #define CONFIG_CMD_MII | |
740 | #define CONFIG_CMD_DATE | |
741 | #define CONFIG_CMD_ELF | |
742 | #define CONFIG_CMD_SETEXPR | |
743 | #define CONFIG_CMD_REGINFO | |
744 | ||
745 | /* | |
746 | * USB | |
747 | */ | |
748 | #define CONFIG_HAS_FSL_DR_USB | |
749 | ||
750 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
751 | #define CONFIG_USB_EHCI | |
752 | ||
753 | #ifdef CONFIG_USB_EHCI | |
754 | #define CONFIG_CMD_USB | |
755 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
756 | #define CONFIG_USB_EHCI_FSL | |
757 | #define CONFIG_USB_STORAGE | |
758 | #endif | |
759 | #endif | |
760 | ||
761 | #define CONFIG_MMC | |
762 | ||
763 | #ifdef CONFIG_MMC | |
764 | #define CONFIG_FSL_ESDHC | |
765 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
766 | #define CONFIG_CMD_MMC | |
767 | #define CONFIG_GENERIC_MMC | |
768 | #endif | |
769 | ||
770 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ | |
771 | || defined(CONFIG_FSL_SATA) | |
772 | #define CONFIG_CMD_EXT2 | |
773 | #define CONFIG_CMD_FAT | |
774 | #define CONFIG_DOS_PARTITION | |
775 | #endif | |
776 | ||
777 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
778 | ||
779 | /* | |
780 | * Miscellaneous configurable options | |
781 | */ | |
782 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
783 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
784 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
785 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
786 | #if defined(CONFIG_CMD_KGDB) | |
787 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
788 | #else | |
789 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
790 | #endif | |
791 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
792 | /* Print Buffer Size */ | |
793 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
794 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
795 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ | |
796 | ||
797 | /* | |
798 | * For booting Linux, the board info and command line data | |
799 | * have to be in the first 64 MB of memory, since this is | |
800 | * the maximum mapped by the Linux kernel during initialization. | |
801 | */ | |
802 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ | |
803 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
804 | ||
805 | #if defined(CONFIG_CMD_KGDB) | |
806 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
807 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
808 | #endif | |
809 | ||
810 | /* | |
811 | * Environment Configuration | |
812 | */ | |
813 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 814 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 815 | #define CONFIG_BOOTFILE "uImage" |
14aa71e6 LY |
816 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
817 | ||
818 | /* default location for tftp and bootm */ | |
819 | #define CONFIG_LOADADDR 1000000 | |
820 | ||
821 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
822 | #define CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
823 | ||
824 | #define CONFIG_BAUDRATE 115200 | |
825 | ||
826 | #ifdef __SW_BOOT_NOR | |
827 | #define __NOR_RST_CMD \ | |
828 | norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ | |
829 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
830 | #endif | |
831 | #ifdef __SW_BOOT_SPI | |
832 | #define __SPI_RST_CMD \ | |
833 | spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ | |
834 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
835 | #endif | |
836 | #ifdef __SW_BOOT_SD | |
837 | #define __SD_RST_CMD \ | |
838 | sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ | |
839 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
840 | #endif | |
841 | #ifdef __SW_BOOT_NAND | |
842 | #define __NAND_RST_CMD \ | |
843 | nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ | |
844 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
845 | #endif | |
846 | #ifdef __SW_BOOT_PCIE | |
847 | #define __PCIE_RST_CMD \ | |
848 | pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ | |
849 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
850 | #endif | |
851 | ||
852 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
853 | "netdev=eth0\0" \ | |
5368c55d | 854 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
14aa71e6 LY |
855 | "loadaddr=1000000\0" \ |
856 | "bootfile=uImage\0" \ | |
857 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
5368c55d MV |
858 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
859 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
860 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
861 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
862 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
14aa71e6 LY |
863 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
864 | "consoledev=ttyS0\0" \ | |
865 | "ramdiskaddr=2000000\0" \ | |
866 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
867 | "fdtaddr=c00000\0" \ | |
868 | "bdev=sda1\0" \ | |
869 | "jffs2nor=mtdblock3\0" \ | |
870 | "norbootaddr=ef080000\0" \ | |
871 | "norfdtaddr=ef040000\0" \ | |
872 | "jffs2nand=mtdblock9\0" \ | |
873 | "nandbootaddr=100000\0" \ | |
874 | "nandfdtaddr=80000\0" \ | |
875 | "ramdisk_size=120000\0" \ | |
876 | "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ | |
877 | "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ | |
5368c55d MV |
878 | __stringify(__NOR_RST_CMD)"\0" \ |
879 | __stringify(__SPI_RST_CMD)"\0" \ | |
880 | __stringify(__SD_RST_CMD)"\0" \ | |
881 | __stringify(__NAND_RST_CMD)"\0" \ | |
882 | __stringify(__PCIE_RST_CMD)"\0" | |
14aa71e6 LY |
883 | |
884 | #define CONFIG_NFSBOOTCOMMAND \ | |
885 | "setenv bootargs root=/dev/nfs rw " \ | |
886 | "nfsroot=$serverip:$rootpath " \ | |
887 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
888 | "console=$consoledev,$baudrate $othbootargs;" \ | |
889 | "tftp $loadaddr $bootfile;" \ | |
890 | "tftp $fdtaddr $fdtfile;" \ | |
891 | "bootm $loadaddr - $fdtaddr" | |
892 | ||
893 | #define CONFIG_HDBOOT \ | |
894 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
895 | "console=$consoledev,$baudrate $othbootargs;" \ | |
896 | "usb start;" \ | |
897 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
898 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
899 | "bootm $loadaddr - $fdtaddr" | |
900 | ||
901 | #define CONFIG_USB_FAT_BOOT \ | |
902 | "setenv bootargs root=/dev/ram rw " \ | |
903 | "console=$consoledev,$baudrate $othbootargs " \ | |
904 | "ramdisk_size=$ramdisk_size;" \ | |
905 | "usb start;" \ | |
906 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
907 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
908 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
909 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
910 | ||
911 | #define CONFIG_USB_EXT2_BOOT \ | |
912 | "setenv bootargs root=/dev/ram rw " \ | |
913 | "console=$consoledev,$baudrate $othbootargs " \ | |
914 | "ramdisk_size=$ramdisk_size;" \ | |
915 | "usb start;" \ | |
916 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
917 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
918 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
919 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
920 | ||
921 | #define CONFIG_NORBOOT \ | |
922 | "setenv bootargs root=/dev/$jffs2nor rw " \ | |
923 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
924 | "bootm $norbootaddr - $norfdtaddr" | |
925 | ||
926 | #define CONFIG_RAMBOOTCOMMAND \ | |
927 | "setenv bootargs root=/dev/ram rw " \ | |
928 | "console=$consoledev,$baudrate $othbootargs " \ | |
929 | "ramdisk_size=$ramdisk_size;" \ | |
930 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
931 | "tftp $loadaddr $bootfile;" \ | |
932 | "tftp $fdtaddr $fdtfile;" \ | |
933 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
934 | ||
935 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
936 | ||
937 | #endif /* __CONFIG_H */ |