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14aa71e6 LY |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * QorIQ RDB boards configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #ifdef CONFIG_36BIT | |
30 | #define CONFIG_PHYS_64BIT | |
31 | #endif | |
32 | ||
33 | #if defined(CONFIG_P1020MBG) | |
e2c91b95 | 34 | #define CONFIG_BOARDNAME "P1020MBG-PC" |
14aa71e6 LY |
35 | #define CONFIG_P1020 |
36 | #define CONFIG_VSC7385_ENET | |
37 | #define CONFIG_SLIC | |
38 | #define __SW_BOOT_MASK 0x03 | |
39 | #define __SW_BOOT_NOR 0xe4 | |
40 | #define __SW_BOOT_SD 0x54 | |
13d1143f | 41 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
42 | #endif |
43 | ||
44 | #if defined(CONFIG_P1020UTM) | |
e2c91b95 | 45 | #define CONFIG_BOARDNAME "P1020UTM-PC" |
14aa71e6 LY |
46 | #define CONFIG_P1020 |
47 | #define __SW_BOOT_MASK 0x03 | |
48 | #define __SW_BOOT_NOR 0xe0 | |
49 | #define __SW_BOOT_SD 0x50 | |
13d1143f | 50 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
51 | #endif |
52 | ||
53 | #if defined(CONFIG_P1020RDB) | |
e2c91b95 | 54 | #define CONFIG_BOARDNAME "P1020RDB-PC" |
14aa71e6 LY |
55 | #define CONFIG_NAND_FSL_ELBC |
56 | #define CONFIG_P1020 | |
57 | #define CONFIG_SPI_FLASH | |
58 | #define CONFIG_VSC7385_ENET | |
59 | #define CONFIG_SLIC | |
60 | #define __SW_BOOT_MASK 0x03 | |
61 | #define __SW_BOOT_NOR 0x5c | |
62 | #define __SW_BOOT_SPI 0x1c | |
63 | #define __SW_BOOT_SD 0x9c | |
64 | #define __SW_BOOT_NAND 0xec | |
65 | #define __SW_BOOT_PCIE 0x6c | |
13d1143f | 66 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
67 | #endif |
68 | ||
69 | #if defined(CONFIG_P1021RDB) | |
e2c91b95 | 70 | #define CONFIG_BOARDNAME "P1021RDB-PC" |
14aa71e6 LY |
71 | #define CONFIG_NAND_FSL_ELBC |
72 | #define CONFIG_P1021 | |
73 | #define CONFIG_QE | |
74 | #define CONFIG_SPI_FLASH | |
75 | #define CONFIG_VSC7385_ENET | |
76 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
77 | addresses in the LBC */ | |
78 | #define __SW_BOOT_MASK 0x03 | |
79 | #define __SW_BOOT_NOR 0x5c | |
80 | #define __SW_BOOT_SPI 0x1c | |
81 | #define __SW_BOOT_SD 0x9c | |
82 | #define __SW_BOOT_NAND 0xec | |
83 | #define __SW_BOOT_PCIE 0x6c | |
13d1143f | 84 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
85 | #endif |
86 | ||
87 | #if defined(CONFIG_P1024RDB) | |
88 | #define CONFIG_BOARDNAME "P1024RDB" | |
89 | #define CONFIG_NAND_FSL_ELBC | |
90 | #define CONFIG_P1024 | |
91 | #define CONFIG_SLIC | |
92 | #define CONFIG_SPI_FLASH | |
93 | #define __SW_BOOT_MASK 0xf3 | |
94 | #define __SW_BOOT_NOR 0x00 | |
95 | #define __SW_BOOT_SPI 0x08 | |
96 | #define __SW_BOOT_SD 0x04 | |
97 | #define __SW_BOOT_NAND 0x0c | |
13d1143f | 98 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
99 | #endif |
100 | ||
101 | #if defined(CONFIG_P1025RDB) | |
102 | #define CONFIG_BOARDNAME "P1025RDB" | |
103 | #define CONFIG_NAND_FSL_ELBC | |
104 | #define CONFIG_P1025 | |
105 | #define CONFIG_QE | |
106 | #define CONFIG_SLIC | |
107 | #define CONFIG_SPI_FLASH | |
108 | ||
109 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
110 | addresses in the LBC */ | |
111 | #define __SW_BOOT_MASK 0xf3 | |
112 | #define __SW_BOOT_NOR 0x00 | |
113 | #define __SW_BOOT_SPI 0x08 | |
114 | #define __SW_BOOT_SD 0x04 | |
115 | #define __SW_BOOT_NAND 0x0c | |
13d1143f | 116 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
14aa71e6 LY |
117 | #endif |
118 | ||
119 | #if defined(CONFIG_P2020RDB) | |
e2c91b95 | 120 | #define CONFIG_BOARDNAME "P2020RDB-PCA" |
14aa71e6 LY |
121 | #define CONFIG_NAND_FSL_ELBC |
122 | #define CONFIG_P2020 | |
123 | #define CONFIG_SPI_FLASH | |
124 | #define CONFIG_VSC7385_ENET | |
125 | #define __SW_BOOT_MASK 0x03 | |
126 | #define __SW_BOOT_NOR 0xc8 | |
127 | #define __SW_BOOT_SPI 0x28 | |
128 | #define __SW_BOOT_SD 0x68 /* or 0x18 */ | |
129 | #define __SW_BOOT_NAND 0xe8 | |
130 | #define __SW_BOOT_PCIE 0xa8 | |
13d1143f SW |
131 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
132 | #endif | |
133 | ||
134 | #if CONFIG_SYS_L2_SIZE >= (512 << 10) | |
135 | /* must be 32-bit */ | |
136 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
137 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
138 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
14aa71e6 LY |
139 | #endif |
140 | ||
141 | #ifdef CONFIG_SDCARD | |
142 | #define CONFIG_RAMBOOT_SDCARD | |
143 | #define CONFIG_SYS_RAMBOOT | |
144 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
145 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
146 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
147 | #endif | |
148 | ||
149 | #ifdef CONFIG_SPIFLASH | |
150 | #define CONFIG_RAMBOOT_SPIFLASH | |
151 | #define CONFIG_SYS_RAMBOOT | |
152 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
153 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
154 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
155 | #endif | |
156 | ||
a796e72c SW |
157 | #ifdef CONFIG_NAND |
158 | #define CONFIG_SPL | |
159 | #define CONFIG_SPL_INIT_MINIMAL | |
160 | #define CONFIG_SPL_SERIAL_SUPPORT | |
161 | #define CONFIG_SPL_NAND_SUPPORT | |
162 | #define CONFIG_SPL_NAND_MINIMAL | |
163 | #define CONFIG_SPL_FLUSH_IMAGE | |
164 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
165 | ||
a796e72c | 166 | #define CONFIG_SPL_TEXT_BASE 0xfffff000 |
6113d3f2 | 167 | #define CONFIG_SPL_MAX_SIZE 4096 |
13d1143f SW |
168 | |
169 | #ifdef CONFIG_SYS_INIT_L2_ADDR | |
170 | /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ | |
171 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 | |
172 | #define CONFIG_SPL_RELOC_TEXT_BASE \ | |
173 | (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) | |
174 | #define CONFIG_SPL_RELOC_STACK \ | |
175 | (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) | |
176 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
177 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
178 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) | |
179 | #else | |
180 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
a796e72c SW |
181 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 |
182 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
a796e72c SW |
183 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
184 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
13d1143f SW |
185 | #endif |
186 | ||
187 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
a796e72c SW |
188 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 |
189 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
14aa71e6 LY |
190 | #endif |
191 | ||
192 | #ifndef CONFIG_SYS_TEXT_BASE | |
193 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
194 | #endif | |
195 | ||
196 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
197 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
198 | #endif | |
199 | ||
200 | #ifndef CONFIG_SYS_MONITOR_BASE | |
a796e72c SW |
201 | #ifdef CONFIG_SPL_BUILD |
202 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
203 | #else | |
14aa71e6 LY |
204 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
205 | #endif | |
a796e72c | 206 | #endif |
14aa71e6 LY |
207 | |
208 | /* High Level Configuration Options */ | |
209 | #define CONFIG_BOOKE | |
210 | #define CONFIG_E500 | |
211 | #define CONFIG_MPC85xx | |
212 | ||
213 | #define CONFIG_MP | |
214 | ||
215 | #define CONFIG_FSL_ELBC | |
216 | #define CONFIG_PCI | |
217 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
218 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
219 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
220 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
221 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
222 | ||
223 | #define CONFIG_FSL_LAW | |
224 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
225 | #define CONFIG_ENV_OVERWRITE | |
226 | ||
227 | #define CONFIG_CMD_SATA | |
befb7d9f | 228 | #define CONFIG_SATA_SIL |
14aa71e6 LY |
229 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
230 | #define CONFIG_LIBATA | |
231 | #define CONFIG_LBA48 | |
232 | ||
233 | #if defined(CONFIG_P2020RDB) | |
234 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
235 | #else | |
236 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
237 | #endif | |
238 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
239 | ||
240 | #define CONFIG_HWCONFIG | |
241 | /* | |
242 | * These can be toggled for performance analysis, otherwise use default. | |
243 | */ | |
244 | #define CONFIG_L2_CACHE | |
245 | #define CONFIG_BTB | |
246 | ||
247 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
babb348c | 248 | |
14aa71e6 | 249 | #define CONFIG_ENABLE_36BIT_PHYS |
14aa71e6 LY |
250 | |
251 | #ifdef CONFIG_PHYS_64BIT | |
252 | #define CONFIG_ADDR_MAP 1 | |
253 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
254 | #endif | |
255 | ||
256 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
257 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
258 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
259 | ||
260 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
261 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
262 | ||
263 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k | |
264 | SPL code*/ | |
a796e72c | 265 | #ifdef CONFIG_SPL_BUILD |
14aa71e6 LY |
266 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
267 | #endif | |
268 | ||
269 | /* DDR Setup */ | |
270 | #define CONFIG_FSL_DDR3 | |
1ba62f10 | 271 | #define CONFIG_SYS_DDR_RAW_TIMING |
14aa71e6 LY |
272 | #define CONFIG_DDR_SPD |
273 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
274 | #define SPD_EEPROM_ADDRESS 0x52 | |
6f5e1dc5 | 275 | #undef CONFIG_FSL_DDR_INTERACTIVE |
14aa71e6 LY |
276 | |
277 | #ifdef CONFIG_P1020MBG | |
278 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G | |
279 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
280 | #else | |
281 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G | |
282 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
283 | #endif | |
284 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) | |
285 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
286 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
287 | ||
288 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
289 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
290 | ||
291 | /* Default settings for DDR3 */ | |
13d1143f | 292 | #ifndef CONFIG_P2020RDB |
14aa71e6 LY |
293 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
294 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
295 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
296 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f | |
297 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 | |
298 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 | |
299 | ||
300 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
301 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
302 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
303 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
304 | ||
305 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
306 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 | |
307 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
308 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
309 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
310 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ | |
311 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 | |
312 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
313 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
314 | ||
315 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
316 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
317 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 | |
318 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF | |
319 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
320 | #define CONFIG_SYS_DDR_MODE_1 0x40461520 | |
321 | #define CONFIG_SYS_DDR_MODE_2 0x8000c000 | |
322 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 | |
323 | #endif | |
324 | ||
325 | #undef CONFIG_CLOCKS_IN_MHZ | |
326 | ||
327 | /* | |
328 | * Memory map | |
329 | * | |
d674bccf | 330 | * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable |
14aa71e6 | 331 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) |
d674bccf | 332 | * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 |
13d1143f SW |
333 | * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable |
334 | * (early boot only) | |
d674bccf SW |
335 | * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 |
336 | * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 | |
337 | * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 | |
338 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 | |
14aa71e6 | 339 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
d674bccf | 340 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable |
d674bccf | 341 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
14aa71e6 LY |
342 | */ |
343 | ||
344 | ||
345 | /* | |
346 | * Local Bus Definitions | |
347 | */ | |
348 | #if defined(CONFIG_P1020MBG) | |
349 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ | |
350 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
351 | #elif defined(CONFIG_P1020UTM) | |
352 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
353 | #define CONFIG_SYS_FLASH_BASE 0xee000000 | |
354 | #else | |
355 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ | |
356 | #define CONFIG_SYS_FLASH_BASE 0xef000000 | |
357 | #endif | |
358 | ||
359 | ||
360 | #ifdef CONFIG_PHYS_64BIT | |
361 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
362 | #else | |
363 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
364 | #endif | |
365 | ||
7ee41107 | 366 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
14aa71e6 LY |
367 | | BR_PS_16 | BR_V) |
368 | ||
369 | #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 | |
370 | ||
371 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
372 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
373 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
374 | ||
375 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
376 | ||
377 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
378 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
379 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
380 | ||
381 | #define CONFIG_FLASH_CFI_DRIVER | |
382 | #define CONFIG_SYS_FLASH_CFI | |
383 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
384 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
385 | ||
386 | /* Nand Flash */ | |
387 | #ifdef CONFIG_NAND_FSL_ELBC | |
388 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
389 | #ifdef CONFIG_PHYS_64BIT | |
390 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
391 | #else | |
392 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
393 | #endif | |
394 | ||
395 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
396 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
397 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
398 | #define CONFIG_CMD_NAND | |
399 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
400 | ||
7ee41107 | 401 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
14aa71e6 LY |
402 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
403 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
404 | | BR_MS_FCM /* MSEL = FCM */ \ | |
405 | | BR_V) /* valid */ | |
406 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ | |
407 | | OR_FCM_CSCT \ | |
408 | | OR_FCM_CST \ | |
409 | | OR_FCM_CHT \ | |
410 | | OR_FCM_SCY_1 \ | |
411 | | OR_FCM_TRLX \ | |
412 | | OR_FCM_EHTR) | |
413 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
414 | ||
415 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
416 | ||
417 | #define CONFIG_SYS_INIT_RAM_LOCK | |
418 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
419 | #ifdef CONFIG_PHYS_64BIT | |
420 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
421 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
422 | /* The assembler doesn't like typecast */ | |
423 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
424 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
425 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
426 | #else | |
427 | /* Initial L1 address */ | |
428 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
429 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
430 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
431 | #endif | |
432 | /* Size of used area in RAM */ | |
433 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
434 | ||
435 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
436 | GENERATED_GBL_DATA_SIZE) | |
437 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
438 | ||
439 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ | |
440 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ | |
441 | ||
442 | #define CONFIG_SYS_CPLD_BASE 0xffa00000 | |
443 | #ifdef CONFIG_PHYS_64BIT | |
444 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull | |
445 | #else | |
446 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
447 | #endif | |
448 | /* CPLD config size: 1Mb */ | |
449 | #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ | |
450 | BR_PS_8 | BR_V) | |
451 | #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) | |
452 | ||
453 | #define CONFIG_SYS_PMC_BASE 0xff980000 | |
454 | #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE | |
455 | #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ | |
456 | BR_PS_8 | BR_V) | |
457 | #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
458 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ | |
459 | OR_GPCM_EAD) | |
460 | ||
a796e72c | 461 | #ifdef CONFIG_NAND |
14aa71e6 LY |
462 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ |
463 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
464 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
465 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
466 | #else | |
467 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
468 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
469 | #ifdef CONFIG_NAND_FSL_ELBC | |
470 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ | |
471 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
472 | #endif | |
473 | #endif | |
474 | #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ | |
475 | #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ | |
476 | ||
477 | ||
478 | /* Vsc7385 switch */ | |
479 | #ifdef CONFIG_VSC7385_ENET | |
480 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
481 | ||
482 | #ifdef CONFIG_PHYS_64BIT | |
483 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
484 | #else | |
485 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE | |
486 | #endif | |
487 | ||
488 | #define CONFIG_SYS_VSC7385_BR_PRELIM \ | |
489 | (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) | |
490 | #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ | |
491 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ | |
492 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
493 | ||
494 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM | |
495 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM | |
496 | ||
497 | /* The size of the VSC7385 firmware image */ | |
498 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
499 | #endif | |
500 | ||
501 | /* Serial Port - controlled on board with jumper J8 | |
502 | * open - index 2 | |
503 | * shorted - index 1 | |
504 | */ | |
505 | #define CONFIG_CONS_INDEX 1 | |
506 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
507 | #define CONFIG_SYS_NS16550 | |
508 | #define CONFIG_SYS_NS16550_SERIAL | |
509 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
510 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
a796e72c | 511 | #ifdef CONFIG_SPL_BUILD |
14aa71e6 LY |
512 | #define CONFIG_NS16550_MIN_FUNCTIONS |
513 | #endif | |
514 | ||
515 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
516 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
517 | ||
518 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
519 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
520 | ||
521 | /* Use the HUSH parser */ | |
522 | #define CONFIG_SYS_HUSH_PARSER | |
14aa71e6 LY |
523 | |
524 | /* | |
525 | * Pass open firmware flat tree | |
526 | */ | |
527 | #define CONFIG_OF_LIBFDT | |
528 | #define CONFIG_OF_BOARD_SETUP | |
529 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
530 | ||
14aa71e6 LY |
531 | /* new uImage format support */ |
532 | #define CONFIG_FIT | |
533 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
534 | ||
535 | /* I2C */ | |
536 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
537 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
538 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
539 | #define CONFIG_I2C_MULTI_BUS | |
540 | #define CONFIG_I2C_CMD_TREE | |
541 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ | |
542 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
543 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
544 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ | |
545 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
546 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
547 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ | |
548 | ||
549 | /* | |
550 | * I2C2 EEPROM | |
551 | */ | |
552 | #undef CONFIG_ID_EEPROM | |
553 | ||
554 | #define CONFIG_RTC_PT7C4338 | |
555 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
556 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 | |
557 | ||
558 | /* enable read and write access to EEPROM */ | |
559 | #define CONFIG_CMD_EEPROM | |
560 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
561 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
562 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
563 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
564 | ||
565 | /* | |
566 | * eSPI - Enhanced SPI | |
567 | */ | |
568 | #define CONFIG_HARD_SPI | |
569 | #define CONFIG_FSL_ESPI | |
570 | ||
571 | #if defined(CONFIG_SPI_FLASH) | |
572 | #define CONFIG_SPI_FLASH_SPANSION | |
573 | #define CONFIG_CMD_SF | |
574 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
575 | #define CONFIG_SF_DEFAULT_MODE 0 | |
576 | #endif | |
577 | ||
578 | #if defined(CONFIG_PCI) | |
579 | /* | |
580 | * General PCI | |
581 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
582 | */ | |
583 | ||
584 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
585 | #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" | |
586 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
587 | #ifdef CONFIG_PHYS_64BIT | |
588 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
589 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
590 | #else | |
591 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
592 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
593 | #endif | |
594 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
595 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
596 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
597 | #ifdef CONFIG_PHYS_64BIT | |
598 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
599 | #else | |
600 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
601 | #endif | |
602 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
603 | ||
604 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
605 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" | |
606 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
607 | #ifdef CONFIG_PHYS_64BIT | |
608 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
609 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
610 | #else | |
611 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
612 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
613 | #endif | |
614 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
615 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
616 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
617 | #ifdef CONFIG_PHYS_64BIT | |
618 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
619 | #else | |
620 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
621 | #endif | |
622 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
623 | ||
14aa71e6 LY |
624 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
625 | #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ | |
626 | #define CONFIG_CMD_PCI | |
627 | #define CONFIG_CMD_NET | |
628 | ||
629 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
630 | #define CONFIG_DOS_PARTITION | |
631 | #endif /* CONFIG_PCI */ | |
632 | ||
633 | #if defined(CONFIG_TSEC_ENET) | |
14aa71e6 LY |
634 | #define CONFIG_MII /* MII PHY management */ |
635 | #define CONFIG_TSEC1 | |
636 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
637 | #define CONFIG_TSEC2 | |
638 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
639 | #define CONFIG_TSEC3 | |
640 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
641 | ||
642 | #define TSEC1_PHY_ADDR 2 | |
643 | #define TSEC2_PHY_ADDR 0 | |
644 | #define TSEC3_PHY_ADDR 1 | |
645 | ||
646 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
647 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
648 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
649 | ||
650 | #define TSEC1_PHYIDX 0 | |
651 | #define TSEC2_PHYIDX 0 | |
652 | #define TSEC3_PHYIDX 0 | |
653 | ||
654 | #define CONFIG_ETHPRIME "eTSEC1" | |
655 | ||
656 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
657 | ||
658 | #define CONFIG_HAS_ETH0 | |
659 | #define CONFIG_HAS_ETH1 | |
660 | #define CONFIG_HAS_ETH2 | |
661 | #endif /* CONFIG_TSEC_ENET */ | |
662 | ||
663 | #ifdef CONFIG_QE | |
664 | /* QE microcode/firmware address */ | |
f2717b47 TT |
665 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
666 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 | |
667 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
14aa71e6 LY |
668 | #endif /* CONFIG_QE */ |
669 | ||
670 | #ifdef CONFIG_P1025RDB | |
671 | /* | |
672 | * QE UEC ethernet configuration | |
673 | */ | |
674 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
675 | ||
676 | #undef CONFIG_UEC_ETH | |
677 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
678 | ||
679 | #define CONFIG_UEC_ETH1 /* ETH1 */ | |
680 | #define CONFIG_HAS_ETH0 | |
681 | ||
682 | #ifdef CONFIG_UEC_ETH1 | |
683 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
684 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ | |
685 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ | |
686 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
687 | #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ | |
688 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
689 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 | |
690 | #endif /* CONFIG_UEC_ETH1 */ | |
691 | ||
692 | #define CONFIG_UEC_ETH5 /* ETH5 */ | |
693 | #define CONFIG_HAS_ETH1 | |
694 | ||
695 | #ifdef CONFIG_UEC_ETH5 | |
696 | #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ | |
697 | #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE | |
698 | #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ | |
699 | #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH | |
700 | #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ | |
701 | #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
702 | #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 | |
703 | #endif /* CONFIG_UEC_ETH5 */ | |
704 | #endif /* CONFIG_P1025RDB */ | |
705 | ||
706 | /* | |
707 | * Environment | |
708 | */ | |
14aa71e6 LY |
709 | #ifdef CONFIG_RAMBOOT_SPIFLASH |
710 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
711 | #define CONFIG_ENV_SPI_BUS 0 | |
712 | #define CONFIG_ENV_SPI_CS 0 | |
713 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
714 | #define CONFIG_ENV_SPI_MODE 0 | |
715 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
716 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
717 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
718 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
719 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 720 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
14aa71e6 LY |
721 | #define CONFIG_ENV_SIZE 0x2000 |
722 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
a796e72c | 723 | #elif defined(CONFIG_NAND) |
14aa71e6 LY |
724 | #define CONFIG_ENV_IS_IN_NAND |
725 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
726 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
727 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) | |
a796e72c | 728 | #elif defined(CONFIG_SYS_RAMBOOT) |
14aa71e6 LY |
729 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
730 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
731 | #define CONFIG_ENV_SIZE 0x2000 | |
14aa71e6 LY |
732 | #else |
733 | #define CONFIG_ENV_IS_IN_FLASH | |
734 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
735 | #define CONFIG_ENV_ADDR 0xfff80000 | |
736 | #else | |
737 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
738 | #endif | |
739 | #define CONFIG_ENV_SIZE 0x2000 | |
740 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
741 | #endif | |
742 | ||
743 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
744 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
745 | ||
746 | /* | |
747 | * Command line configuration. | |
748 | */ | |
749 | #include <config_cmd_default.h> | |
750 | ||
751 | #define CONFIG_CMD_IRQ | |
752 | #define CONFIG_CMD_PING | |
753 | #define CONFIG_CMD_I2C | |
754 | #define CONFIG_CMD_MII | |
755 | #define CONFIG_CMD_DATE | |
756 | #define CONFIG_CMD_ELF | |
757 | #define CONFIG_CMD_SETEXPR | |
758 | #define CONFIG_CMD_REGINFO | |
759 | ||
760 | /* | |
761 | * USB | |
762 | */ | |
763 | #define CONFIG_HAS_FSL_DR_USB | |
764 | ||
765 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
766 | #define CONFIG_USB_EHCI | |
767 | ||
768 | #ifdef CONFIG_USB_EHCI | |
769 | #define CONFIG_CMD_USB | |
770 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
771 | #define CONFIG_USB_EHCI_FSL | |
772 | #define CONFIG_USB_STORAGE | |
773 | #endif | |
774 | #endif | |
775 | ||
776 | #define CONFIG_MMC | |
777 | ||
778 | #ifdef CONFIG_MMC | |
779 | #define CONFIG_FSL_ESDHC | |
780 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
781 | #define CONFIG_CMD_MMC | |
782 | #define CONFIG_GENERIC_MMC | |
783 | #endif | |
784 | ||
785 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ | |
786 | || defined(CONFIG_FSL_SATA) | |
787 | #define CONFIG_CMD_EXT2 | |
788 | #define CONFIG_CMD_FAT | |
789 | #define CONFIG_DOS_PARTITION | |
790 | #endif | |
791 | ||
792 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
793 | ||
794 | /* | |
795 | * Miscellaneous configurable options | |
796 | */ | |
797 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
798 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
799 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
800 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
801 | #if defined(CONFIG_CMD_KGDB) | |
802 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
803 | #else | |
804 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
805 | #endif | |
806 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
807 | /* Print Buffer Size */ | |
808 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
809 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
810 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ | |
811 | ||
812 | /* | |
813 | * For booting Linux, the board info and command line data | |
814 | * have to be in the first 64 MB of memory, since this is | |
815 | * the maximum mapped by the Linux kernel during initialization. | |
816 | */ | |
817 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ | |
818 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
819 | ||
820 | #if defined(CONFIG_CMD_KGDB) | |
821 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
822 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
823 | #endif | |
824 | ||
825 | /* | |
826 | * Environment Configuration | |
827 | */ | |
828 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 829 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 830 | #define CONFIG_BOOTFILE "uImage" |
14aa71e6 LY |
831 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
832 | ||
833 | /* default location for tftp and bootm */ | |
834 | #define CONFIG_LOADADDR 1000000 | |
835 | ||
836 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
837 | #define CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
838 | ||
839 | #define CONFIG_BAUDRATE 115200 | |
840 | ||
841 | #ifdef __SW_BOOT_NOR | |
842 | #define __NOR_RST_CMD \ | |
843 | norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ | |
844 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
845 | #endif | |
846 | #ifdef __SW_BOOT_SPI | |
847 | #define __SPI_RST_CMD \ | |
848 | spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ | |
849 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
850 | #endif | |
851 | #ifdef __SW_BOOT_SD | |
852 | #define __SD_RST_CMD \ | |
853 | sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ | |
854 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
855 | #endif | |
856 | #ifdef __SW_BOOT_NAND | |
857 | #define __NAND_RST_CMD \ | |
858 | nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ | |
859 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
860 | #endif | |
861 | #ifdef __SW_BOOT_PCIE | |
862 | #define __PCIE_RST_CMD \ | |
863 | pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ | |
864 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
865 | #endif | |
866 | ||
867 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
868 | "netdev=eth0\0" \ | |
5368c55d | 869 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
14aa71e6 LY |
870 | "loadaddr=1000000\0" \ |
871 | "bootfile=uImage\0" \ | |
872 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
5368c55d MV |
873 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
874 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
875 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
876 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
877 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
14aa71e6 LY |
878 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
879 | "consoledev=ttyS0\0" \ | |
880 | "ramdiskaddr=2000000\0" \ | |
881 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
882 | "fdtaddr=c00000\0" \ | |
883 | "bdev=sda1\0" \ | |
884 | "jffs2nor=mtdblock3\0" \ | |
885 | "norbootaddr=ef080000\0" \ | |
886 | "norfdtaddr=ef040000\0" \ | |
887 | "jffs2nand=mtdblock9\0" \ | |
888 | "nandbootaddr=100000\0" \ | |
889 | "nandfdtaddr=80000\0" \ | |
890 | "ramdisk_size=120000\0" \ | |
891 | "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ | |
892 | "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ | |
5368c55d MV |
893 | __stringify(__NOR_RST_CMD)"\0" \ |
894 | __stringify(__SPI_RST_CMD)"\0" \ | |
895 | __stringify(__SD_RST_CMD)"\0" \ | |
896 | __stringify(__NAND_RST_CMD)"\0" \ | |
897 | __stringify(__PCIE_RST_CMD)"\0" | |
14aa71e6 LY |
898 | |
899 | #define CONFIG_NFSBOOTCOMMAND \ | |
900 | "setenv bootargs root=/dev/nfs rw " \ | |
901 | "nfsroot=$serverip:$rootpath " \ | |
902 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
903 | "console=$consoledev,$baudrate $othbootargs;" \ | |
904 | "tftp $loadaddr $bootfile;" \ | |
905 | "tftp $fdtaddr $fdtfile;" \ | |
906 | "bootm $loadaddr - $fdtaddr" | |
907 | ||
908 | #define CONFIG_HDBOOT \ | |
909 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
910 | "console=$consoledev,$baudrate $othbootargs;" \ | |
911 | "usb start;" \ | |
912 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
913 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
914 | "bootm $loadaddr - $fdtaddr" | |
915 | ||
916 | #define CONFIG_USB_FAT_BOOT \ | |
917 | "setenv bootargs root=/dev/ram rw " \ | |
918 | "console=$consoledev,$baudrate $othbootargs " \ | |
919 | "ramdisk_size=$ramdisk_size;" \ | |
920 | "usb start;" \ | |
921 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
922 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
923 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
924 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
925 | ||
926 | #define CONFIG_USB_EXT2_BOOT \ | |
927 | "setenv bootargs root=/dev/ram rw " \ | |
928 | "console=$consoledev,$baudrate $othbootargs " \ | |
929 | "ramdisk_size=$ramdisk_size;" \ | |
930 | "usb start;" \ | |
931 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
932 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
933 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
934 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
935 | ||
936 | #define CONFIG_NORBOOT \ | |
937 | "setenv bootargs root=/dev/$jffs2nor rw " \ | |
938 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
939 | "bootm $norbootaddr - $norfdtaddr" | |
940 | ||
941 | #define CONFIG_RAMBOOTCOMMAND \ | |
942 | "setenv bootargs root=/dev/ram rw " \ | |
943 | "console=$consoledev,$baudrate $othbootargs " \ | |
944 | "ramdisk_size=$ramdisk_size;" \ | |
945 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
946 | "tftp $loadaddr $bootfile;" \ | |
947 | "tftp $fdtaddr $fdtfile;" \ | |
948 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
949 | ||
950 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
951 | ||
952 | #endif /* __CONFIG_H */ |