projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 14aa71e6 LY |
1 | /* |
| 2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 14aa71e6 LY |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * QorIQ RDB boards configuration file | |
| 9 | */ | |
| 10 | #ifndef __CONFIG_H | |
| 11 | #define __CONFIG_H | |
| 12 | ||
| fedae6eb | 13 | #if defined(CONFIG_TARGET_P1020MBG) |
| e2c91b95 | 14 | #define CONFIG_BOARDNAME "P1020MBG-PC" |
| 14aa71e6 LY |
15 | #define CONFIG_VSC7385_ENET |
| 16 | #define CONFIG_SLIC | |
| 17 | #define __SW_BOOT_MASK 0x03 | |
| 18 | #define __SW_BOOT_NOR 0xe4 | |
| 19 | #define __SW_BOOT_SD 0x54 | |
| 13d1143f | 20 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 14aa71e6 LY |
21 | #endif |
| 22 | ||
| e9bc8a8f | 23 | #if defined(CONFIG_TARGET_P1020UTM) |
| e2c91b95 | 24 | #define CONFIG_BOARDNAME "P1020UTM-PC" |
| 14aa71e6 LY |
25 | #define __SW_BOOT_MASK 0x03 |
| 26 | #define __SW_BOOT_NOR 0xe0 | |
| 27 | #define __SW_BOOT_SD 0x50 | |
| 13d1143f | 28 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 14aa71e6 LY |
29 | #endif |
| 30 | ||
| aa14620c | 31 | #if defined(CONFIG_TARGET_P1020RDB_PC) |
| e2c91b95 | 32 | #define CONFIG_BOARDNAME "P1020RDB-PC" |
| 14aa71e6 | 33 | #define CONFIG_NAND_FSL_ELBC |
| 14aa71e6 LY |
34 | #define CONFIG_VSC7385_ENET |
| 35 | #define CONFIG_SLIC | |
| 36 | #define __SW_BOOT_MASK 0x03 | |
| 37 | #define __SW_BOOT_NOR 0x5c | |
| 38 | #define __SW_BOOT_SPI 0x1c | |
| 39 | #define __SW_BOOT_SD 0x9c | |
| 40 | #define __SW_BOOT_NAND 0xec | |
| 41 | #define __SW_BOOT_PCIE 0x6c | |
| 13d1143f | 42 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 14aa71e6 LY |
43 | #endif |
| 44 | ||
| 45fdb627 HZ |
45 | /* |
| 46 | * P1020RDB-PD board has user selectable switches for evaluating different | |
| 47 | * frequency and boot options for the P1020 device. The table that | |
| 48 | * follow describe the available options. The front six binary number was in | |
| 49 | * accordance with SW3[1:6]. | |
| 50 | * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off | |
| 51 | * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off | |
| 52 | * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off | |
| 53 | * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off | |
| 54 | * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off | |
| 55 | * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off | |
| 56 | * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off | |
| 57 | */ | |
| f404b66c | 58 | #if defined(CONFIG_TARGET_P1020RDB_PD) |
| 45fdb627 HZ |
59 | #define CONFIG_BOARDNAME "P1020RDB-PD" |
| 60 | #define CONFIG_NAND_FSL_ELBC | |
| 45fdb627 HZ |
61 | #define CONFIG_VSC7385_ENET |
| 62 | #define CONFIG_SLIC | |
| 63 | #define __SW_BOOT_MASK 0x03 | |
| 64 | #define __SW_BOOT_NOR 0x64 | |
| 65 | #define __SW_BOOT_SPI 0x34 | |
| 66 | #define __SW_BOOT_SD 0x24 | |
| 67 | #define __SW_BOOT_NAND 0x44 | |
| 68 | #define __SW_BOOT_PCIE 0x74 | |
| 69 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 94b383e7 YL |
70 | /* |
| 71 | * Dynamic MTD Partition support with mtdparts | |
| 72 | */ | |
| 73 | #define CONFIG_MTD_DEVICE | |
| 74 | #define CONFIG_MTD_PARTITIONS | |
| 75 | #define CONFIG_CMD_MTDPARTS | |
| 76 | #define CONFIG_FLASH_CFI_MTD | |
| 77 | #define MTDIDS_DEFAULT "nor0=ec000000.nor" | |
| 78 | #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ | |
| 79 | "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" | |
| 45fdb627 HZ |
80 | #endif |
| 81 | ||
| da439db3 | 82 | #if defined(CONFIG_TARGET_P1021RDB) |
| e2c91b95 | 83 | #define CONFIG_BOARDNAME "P1021RDB-PC" |
| 14aa71e6 | 84 | #define CONFIG_NAND_FSL_ELBC |
| 14aa71e6 | 85 | #define CONFIG_QE |
| 14aa71e6 LY |
86 | #define CONFIG_VSC7385_ENET |
| 87 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
| 88 | addresses in the LBC */ | |
| 89 | #define __SW_BOOT_MASK 0x03 | |
| 90 | #define __SW_BOOT_NOR 0x5c | |
| 91 | #define __SW_BOOT_SPI 0x1c | |
| 92 | #define __SW_BOOT_SD 0x9c | |
| 93 | #define __SW_BOOT_NAND 0xec | |
| 94 | #define __SW_BOOT_PCIE 0x6c | |
| 13d1143f | 95 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 94b383e7 YL |
96 | /* |
| 97 | * Dynamic MTD Partition support with mtdparts | |
| 98 | */ | |
| 99 | #define CONFIG_MTD_DEVICE | |
| 100 | #define CONFIG_MTD_PARTITIONS | |
| 101 | #define CONFIG_CMD_MTDPARTS | |
| 102 | #define CONFIG_FLASH_CFI_MTD | |
| 103 | #ifdef CONFIG_PHYS_64BIT | |
| 104 | #define MTDIDS_DEFAULT "nor0=fef000000.nor" | |
| 105 | #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ | |
| 106 | "256k(dtb),4608k(kernel),9728k(fs)," \ | |
| 107 | "256k(qe-ucode-firmware),1280k(u-boot)" | |
| 108 | #else | |
| 109 | #define MTDIDS_DEFAULT "nor0=ef000000.nor" | |
| 110 | #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ | |
| 111 | "256k(dtb),4608k(kernel),9728k(fs)," \ | |
| 112 | "256k(qe-ucode-firmware),1280k(u-boot)" | |
| 113 | #endif | |
| 14aa71e6 LY |
114 | #endif |
| 115 | ||
| 4eedabfe | 116 | #if defined(CONFIG_TARGET_P1024RDB) |
| 14aa71e6 LY |
117 | #define CONFIG_BOARDNAME "P1024RDB" |
| 118 | #define CONFIG_NAND_FSL_ELBC | |
| 14aa71e6 | 119 | #define CONFIG_SLIC |
| 14aa71e6 LY |
120 | #define __SW_BOOT_MASK 0xf3 |
| 121 | #define __SW_BOOT_NOR 0x00 | |
| 122 | #define __SW_BOOT_SPI 0x08 | |
| 123 | #define __SW_BOOT_SD 0x04 | |
| 124 | #define __SW_BOOT_NAND 0x0c | |
| 13d1143f | 125 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 14aa71e6 LY |
126 | #endif |
| 127 | ||
| b0c98b4b | 128 | #if defined(CONFIG_TARGET_P1025RDB) |
| 14aa71e6 LY |
129 | #define CONFIG_BOARDNAME "P1025RDB" |
| 130 | #define CONFIG_NAND_FSL_ELBC | |
| 14aa71e6 LY |
131 | #define CONFIG_QE |
| 132 | #define CONFIG_SLIC | |
| 14aa71e6 LY |
133 | |
| 134 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of | |
| 135 | addresses in the LBC */ | |
| 136 | #define __SW_BOOT_MASK 0xf3 | |
| 137 | #define __SW_BOOT_NOR 0x00 | |
| 138 | #define __SW_BOOT_SPI 0x08 | |
| 139 | #define __SW_BOOT_SD 0x04 | |
| 140 | #define __SW_BOOT_NAND 0x0c | |
| 13d1143f | 141 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 14aa71e6 LY |
142 | #endif |
| 143 | ||
| 8435aa77 YS |
144 | #if defined(CONFIG_TARGET_P2020RDB) |
| 145 | #define CONFIG_BOARDNAME "P2020RDB-PC" | |
| 14aa71e6 | 146 | #define CONFIG_NAND_FSL_ELBC |
| 14aa71e6 LY |
147 | #define CONFIG_VSC7385_ENET |
| 148 | #define __SW_BOOT_MASK 0x03 | |
| 149 | #define __SW_BOOT_NOR 0xc8 | |
| 150 | #define __SW_BOOT_SPI 0x28 | |
| 151 | #define __SW_BOOT_SD 0x68 /* or 0x18 */ | |
| 152 | #define __SW_BOOT_NAND 0xe8 | |
| 153 | #define __SW_BOOT_PCIE 0xa8 | |
| 13d1143f | 154 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 94b383e7 YL |
155 | /* |
| 156 | * Dynamic MTD Partition support with mtdparts | |
| 157 | */ | |
| 158 | #define CONFIG_MTD_DEVICE | |
| 159 | #define CONFIG_MTD_PARTITIONS | |
| 160 | #define CONFIG_CMD_MTDPARTS | |
| 161 | #define CONFIG_FLASH_CFI_MTD | |
| 162 | #ifdef CONFIG_PHYS_64BIT | |
| 163 | #define MTDIDS_DEFAULT "nor0=fef000000.nor" | |
| 164 | #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ | |
| 165 | "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" | |
| 166 | #else | |
| 167 | #define MTDIDS_DEFAULT "nor0=ef000000.nor" | |
| 168 | #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ | |
| 169 | "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" | |
| 170 | #endif | |
| 13d1143f SW |
171 | #endif |
| 172 | ||
| 14aa71e6 | 173 | #ifdef CONFIG_SDCARD |
| 3e6e6983 YZ |
174 | #define CONFIG_SPL_MMC_MINIMAL |
| 175 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 176 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 3e6e6983 YZ |
177 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| 178 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| ee4d6511 YZ |
179 | #define CONFIG_SPL_PAD_TO 0x20000 |
| 180 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| e222b1f3 | 181 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 3e6e6983 YZ |
182 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
| 183 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| ee4d6511 | 184 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) |
| 3e6e6983 YZ |
185 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 186 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 187 | #define CONFIG_SPL_MMC_BOOT | |
| 188 | #ifdef CONFIG_SPL_BUILD | |
| 189 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 190 | #endif | |
| 14aa71e6 LY |
191 | #endif |
| 192 | ||
| 193 | #ifdef CONFIG_SPIFLASH | |
| d34e5624 YZ |
194 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 195 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 196 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| d34e5624 YZ |
197 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| 198 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| ee4d6511 YZ |
199 | #define CONFIG_SPL_PAD_TO 0x20000 |
| 200 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| e222b1f3 | 201 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| d34e5624 YZ |
202 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
| 203 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| ee4d6511 | 204 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
| d34e5624 YZ |
205 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 206 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 207 | #define CONFIG_SPL_SPI_BOOT | |
| 208 | #ifdef CONFIG_SPL_BUILD | |
| 209 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 210 | #endif | |
| 14aa71e6 LY |
211 | #endif |
| 212 | ||
| a796e72c | 213 | #ifdef CONFIG_NAND |
| 62c6ef33 YZ |
214 | #ifdef CONFIG_TPL_BUILD |
| 215 | #define CONFIG_SPL_NAND_BOOT | |
| 216 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 62c6ef33 | 217 | #define CONFIG_SPL_NAND_INIT |
| 62c6ef33 YZ |
218 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 219 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| 220 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| 221 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| e222b1f3 | 222 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
| 62c6ef33 YZ |
223 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
| 224 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| 225 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
| 226 | #elif defined(CONFIG_SPL_BUILD) | |
| a796e72c | 227 | #define CONFIG_SPL_INIT_MINIMAL |
| a796e72c SW |
228 | #define CONFIG_SPL_FLUSH_IMAGE |
| 229 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 62c6ef33 | 230 | #define CONFIG_SPL_TEXT_BASE 0xff800000 |
| 6113d3f2 | 231 | #define CONFIG_SPL_MAX_SIZE 4096 |
| 62c6ef33 YZ |
232 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
| 233 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
| 234 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
| 235 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
| 236 | #endif /* not CONFIG_TPL_BUILD */ | |
| 237 | ||
| 238 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 239 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 240 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 241 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
| 242 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 14aa71e6 LY |
243 | #endif |
| 244 | ||
| 245 | #ifndef CONFIG_SYS_TEXT_BASE | |
| e222b1f3 | 246 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| 14aa71e6 LY |
247 | #endif |
| 248 | ||
| 249 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 250 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 251 | #endif | |
| 252 | ||
| 253 | #ifndef CONFIG_SYS_MONITOR_BASE | |
| a796e72c SW |
254 | #ifdef CONFIG_SPL_BUILD |
| 255 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 256 | #else | |
| 14aa71e6 LY |
257 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 258 | #endif | |
| a796e72c | 259 | #endif |
| 14aa71e6 | 260 | |
| 14aa71e6 LY |
261 | #define CONFIG_MP |
| 262 | ||
| b38eaec5 RD |
263 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 264 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 14aa71e6 | 265 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 842033e6 | 266 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| 14aa71e6 LY |
267 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| 268 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 269 | ||
| 14aa71e6 LY |
270 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 271 | #define CONFIG_ENV_OVERWRITE | |
| 272 | ||
| 273 | #define CONFIG_CMD_SATA | |
| befb7d9f | 274 | #define CONFIG_SATA_SIL |
| 14aa71e6 LY |
275 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 276 | #define CONFIG_LIBATA | |
| 277 | #define CONFIG_LBA48 | |
| 278 | ||
| 8435aa77 | 279 | #if defined(CONFIG_TARGET_P2020RDB) |
| 14aa71e6 LY |
280 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 281 | #else | |
| 282 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
| 283 | #endif | |
| 284 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
| 285 | ||
| 286 | #define CONFIG_HWCONFIG | |
| 287 | /* | |
| 288 | * These can be toggled for performance analysis, otherwise use default. | |
| 289 | */ | |
| 290 | #define CONFIG_L2_CACHE | |
| 291 | #define CONFIG_BTB | |
| 292 | ||
| 14aa71e6 | 293 | #define CONFIG_ENABLE_36BIT_PHYS |
| 14aa71e6 LY |
294 | |
| 295 | #ifdef CONFIG_PHYS_64BIT | |
| 296 | #define CONFIG_ADDR_MAP 1 | |
| 297 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 298 | #endif | |
| 299 | ||
| 300 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 301 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
| 302 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 303 | ||
| 304 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 305 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 306 | ||
| 307 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k | |
| 308 | SPL code*/ | |
| a796e72c | 309 | #ifdef CONFIG_SPL_BUILD |
| 14aa71e6 LY |
310 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 311 | #endif | |
| 312 | ||
| 313 | /* DDR Setup */ | |
| 1ba62f10 | 314 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 14aa71e6 LY |
315 | #define CONFIG_DDR_SPD |
| 316 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
| 317 | #define SPD_EEPROM_ADDRESS 0x52 | |
| 6f5e1dc5 | 318 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 14aa71e6 | 319 | |
| f404b66c | 320 | #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) |
| 14aa71e6 LY |
321 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G |
| 322 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 323 | #else | |
| 324 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G | |
| 325 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 326 | #endif | |
| 327 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) | |
| 328 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 329 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 330 | ||
| 14aa71e6 LY |
331 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 332 | ||
| 333 | /* Default settings for DDR3 */ | |
| 8435aa77 | 334 | #ifndef CONFIG_TARGET_P2020RDB |
| 14aa71e6 LY |
335 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
| 336 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 337 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 338 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f | |
| 339 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 | |
| 340 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 | |
| 341 | ||
| 342 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 343 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 344 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 345 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 346 | ||
| 347 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 348 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 | |
| 349 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 350 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 351 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| 352 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ | |
| 353 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 | |
| 354 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
| 355 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 356 | ||
| 357 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 358 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
| 359 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 | |
| 360 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF | |
| 361 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
| 362 | #define CONFIG_SYS_DDR_MODE_1 0x40461520 | |
| 363 | #define CONFIG_SYS_DDR_MODE_2 0x8000c000 | |
| 364 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 | |
| 365 | #endif | |
| 366 | ||
| 367 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 368 | ||
| 369 | /* | |
| 370 | * Memory map | |
| 371 | * | |
| d674bccf | 372 | * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable |
| 14aa71e6 | 373 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) |
| d674bccf | 374 | * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 |
| 13d1143f SW |
375 | * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable |
| 376 | * (early boot only) | |
| d674bccf SW |
377 | * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 |
| 378 | * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 | |
| 379 | * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 | |
| 380 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 | |
| 14aa71e6 | 381 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
| d674bccf | 382 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable |
| d674bccf | 383 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 14aa71e6 LY |
384 | */ |
| 385 | ||
| 14aa71e6 LY |
386 | /* |
| 387 | * Local Bus Definitions | |
| 388 | */ | |
| f404b66c | 389 | #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) |
| 14aa71e6 LY |
390 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ |
| 391 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
| e9bc8a8f | 392 | #elif defined(CONFIG_TARGET_P1020UTM) |
| 14aa71e6 LY |
393 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ |
| 394 | #define CONFIG_SYS_FLASH_BASE 0xee000000 | |
| 395 | #else | |
| 396 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ | |
| 397 | #define CONFIG_SYS_FLASH_BASE 0xef000000 | |
| 398 | #endif | |
| 399 | ||
| 14aa71e6 LY |
400 | #ifdef CONFIG_PHYS_64BIT |
| 401 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 402 | #else | |
| 403 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 404 | #endif | |
| 405 | ||
| 7ee41107 | 406 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 14aa71e6 LY |
407 | | BR_PS_16 | BR_V) |
| 408 | ||
| 409 | #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 | |
| 410 | ||
| 411 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 412 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 413 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 414 | ||
| 415 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 416 | ||
| 417 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 418 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 419 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 420 | ||
| 421 | #define CONFIG_FLASH_CFI_DRIVER | |
| 422 | #define CONFIG_SYS_FLASH_CFI | |
| 423 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 424 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 425 | ||
| 426 | /* Nand Flash */ | |
| 427 | #ifdef CONFIG_NAND_FSL_ELBC | |
| 428 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 429 | #ifdef CONFIG_PHYS_64BIT | |
| 430 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
| 431 | #else | |
| 432 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 433 | #endif | |
| 434 | ||
| 435 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 436 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 14aa71e6 | 437 | #define CONFIG_CMD_NAND |
| f404b66c | 438 | #if defined(CONFIG_TARGET_P1020RDB_PD) |
| 45fdb627 HZ |
439 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 440 | #else | |
| 14aa71e6 | 441 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) |
| 45fdb627 | 442 | #endif |
| 14aa71e6 | 443 | |
| 7ee41107 | 444 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 14aa71e6 LY |
445 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 446 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 447 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 448 | | BR_V) /* valid */ | |
| f404b66c | 449 | #if defined(CONFIG_TARGET_P1020RDB_PD) |
| 45fdb627 HZ |
450 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ |
| 451 | | OR_FCM_PGS /* Large Page*/ \ | |
| 452 | | OR_FCM_CSCT \ | |
| 453 | | OR_FCM_CST \ | |
| 454 | | OR_FCM_CHT \ | |
| 455 | | OR_FCM_SCY_1 \ | |
| 456 | | OR_FCM_TRLX \ | |
| 457 | | OR_FCM_EHTR) | |
| 458 | #else | |
| 14aa71e6 LY |
459 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ |
| 460 | | OR_FCM_CSCT \ | |
| 461 | | OR_FCM_CST \ | |
| 462 | | OR_FCM_CHT \ | |
| 463 | | OR_FCM_SCY_1 \ | |
| 464 | | OR_FCM_TRLX \ | |
| 465 | | OR_FCM_EHTR) | |
| 45fdb627 | 466 | #endif |
| 14aa71e6 LY |
467 | #endif /* CONFIG_NAND_FSL_ELBC */ |
| 468 | ||
| 469 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 470 | ||
| 471 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 472 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| 473 | #ifdef CONFIG_PHYS_64BIT | |
| 474 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| 475 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
| 476 | /* The assembler doesn't like typecast */ | |
| 477 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 478 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 479 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 480 | #else | |
| 481 | /* Initial L1 address */ | |
| 482 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
| 483 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
| 484 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
| 485 | #endif | |
| 486 | /* Size of used area in RAM */ | |
| 487 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 488 | ||
| 489 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 490 | GENERATED_GBL_DATA_SIZE) | |
| 491 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 492 | ||
| 9307cbab | 493 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 14aa71e6 LY |
494 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ |
| 495 | ||
| 496 | #define CONFIG_SYS_CPLD_BASE 0xffa00000 | |
| 497 | #ifdef CONFIG_PHYS_64BIT | |
| 498 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull | |
| 499 | #else | |
| 500 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
| 501 | #endif | |
| 502 | /* CPLD config size: 1Mb */ | |
| 503 | #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ | |
| 504 | BR_PS_8 | BR_V) | |
| 505 | #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) | |
| 506 | ||
| 507 | #define CONFIG_SYS_PMC_BASE 0xff980000 | |
| 508 | #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE | |
| 509 | #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ | |
| 510 | BR_PS_8 | BR_V) | |
| 511 | #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
| 512 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ | |
| 513 | OR_GPCM_EAD) | |
| 514 | ||
| a796e72c | 515 | #ifdef CONFIG_NAND |
| 14aa71e6 LY |
516 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ |
| 517 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 518 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 519 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 520 | #else | |
| 521 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 522 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 523 | #ifdef CONFIG_NAND_FSL_ELBC | |
| 524 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ | |
| 525 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 526 | #endif | |
| 527 | #endif | |
| 528 | #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ | |
| 529 | #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ | |
| 530 | ||
| 14aa71e6 LY |
531 | /* Vsc7385 switch */ |
| 532 | #ifdef CONFIG_VSC7385_ENET | |
| 533 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
| 534 | ||
| 535 | #ifdef CONFIG_PHYS_64BIT | |
| 536 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
| 537 | #else | |
| 538 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE | |
| 539 | #endif | |
| 540 | ||
| 541 | #define CONFIG_SYS_VSC7385_BR_PRELIM \ | |
| 542 | (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) | |
| 543 | #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ | |
| 544 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ | |
| 545 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 546 | ||
| 547 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM | |
| 548 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM | |
| 549 | ||
| 550 | /* The size of the VSC7385 firmware image */ | |
| 551 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
| 552 | #endif | |
| 553 | ||
| 3e6e6983 YZ |
554 | /* |
| 555 | * Config the L2 Cache as L2 SRAM | |
| 556 | */ | |
| 557 | #if defined(CONFIG_SPL_BUILD) | |
| d34e5624 | 558 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
| 3e6e6983 YZ |
559 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 560 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 561 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 562 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 3e6e6983 | 563 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
| 5a89fa92 YZ |
564 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
| 565 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) | |
| 566 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) | |
| 8435aa77 | 567 | #if defined(CONFIG_TARGET_P2020RDB) |
| 5a89fa92 YZ |
568 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) |
| 569 | #else | |
| 570 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) | |
| 571 | #endif | |
| 62c6ef33 YZ |
572 | #elif defined(CONFIG_NAND) |
| 573 | #ifdef CONFIG_TPL_BUILD | |
| 574 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 575 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 576 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 577 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 578 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 579 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 580 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 581 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| 582 | #else | |
| 583 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 584 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 585 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 586 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 587 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 588 | #endif /* CONFIG_TPL_BUILD */ | |
| 3e6e6983 YZ |
589 | #endif |
| 590 | #endif | |
| 591 | ||
| 14aa71e6 LY |
592 | /* Serial Port - controlled on board with jumper J8 |
| 593 | * open - index 2 | |
| 594 | * shorted - index 1 | |
| 595 | */ | |
| 596 | #define CONFIG_CONS_INDEX 1 | |
| 597 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 14aa71e6 LY |
598 | #define CONFIG_SYS_NS16550_SERIAL |
| 599 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 600 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 3e6e6983 | 601 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| 14aa71e6 LY |
602 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 603 | #endif | |
| 604 | ||
| 605 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 606 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 607 | ||
| 608 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 609 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 610 | ||
| 14aa71e6 | 611 | /* I2C */ |
| 00f792e0 HS |
612 | #define CONFIG_SYS_I2C |
| 613 | #define CONFIG_SYS_I2C_FSL | |
| 614 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 615 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 616 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 617 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 618 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 619 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 620 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
| 14aa71e6 | 621 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 14aa71e6 LY |
622 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ |
| 623 | ||
| 624 | /* | |
| 625 | * I2C2 EEPROM | |
| 626 | */ | |
| 627 | #undef CONFIG_ID_EEPROM | |
| 628 | ||
| 629 | #define CONFIG_RTC_PT7C4338 | |
| 630 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 631 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 | |
| 632 | ||
| 633 | /* enable read and write access to EEPROM */ | |
| 634 | #define CONFIG_CMD_EEPROM | |
| 14aa71e6 LY |
635 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 636 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 637 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 638 | ||
| 639 | /* | |
| 640 | * eSPI - Enhanced SPI | |
| 641 | */ | |
| 642 | #define CONFIG_HARD_SPI | |
| 14aa71e6 LY |
643 | |
| 644 | #if defined(CONFIG_SPI_FLASH) | |
| 14aa71e6 LY |
645 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 646 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 647 | #endif | |
| 648 | ||
| 649 | #if defined(CONFIG_PCI) | |
| 650 | /* | |
| 651 | * General PCI | |
| 652 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 653 | */ | |
| 654 | ||
| 655 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
| 656 | #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" | |
| 657 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 658 | #ifdef CONFIG_PHYS_64BIT | |
| 659 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
| 660 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 661 | #else | |
| 662 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 663 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 664 | #endif | |
| 665 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 666 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 667 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 668 | #ifdef CONFIG_PHYS_64BIT | |
| 669 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 670 | #else | |
| 671 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 672 | #endif | |
| 673 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 674 | ||
| 675 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
| 676 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" | |
| 677 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 678 | #ifdef CONFIG_PHYS_64BIT | |
| 679 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 680 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 681 | #else | |
| 682 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 683 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
| 684 | #endif | |
| 685 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 686 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
| 687 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 688 | #ifdef CONFIG_PHYS_64BIT | |
| 689 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 690 | #else | |
| 691 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
| 692 | #endif | |
| 693 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 694 | ||
| 14aa71e6 | 695 | #define CONFIG_CMD_PCI |
| 14aa71e6 LY |
696 | |
| 697 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 14aa71e6 LY |
698 | #endif /* CONFIG_PCI */ |
| 699 | ||
| 700 | #if defined(CONFIG_TSEC_ENET) | |
| 14aa71e6 LY |
701 | #define CONFIG_MII /* MII PHY management */ |
| 702 | #define CONFIG_TSEC1 | |
| 703 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 704 | #define CONFIG_TSEC2 | |
| 705 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 706 | #define CONFIG_TSEC3 | |
| 707 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 708 | ||
| 709 | #define TSEC1_PHY_ADDR 2 | |
| 710 | #define TSEC2_PHY_ADDR 0 | |
| 711 | #define TSEC3_PHY_ADDR 1 | |
| 712 | ||
| 713 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 714 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 715 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 716 | ||
| 717 | #define TSEC1_PHYIDX 0 | |
| 718 | #define TSEC2_PHYIDX 0 | |
| 719 | #define TSEC3_PHYIDX 0 | |
| 720 | ||
| 721 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 722 | ||
| 723 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 724 | ||
| 725 | #define CONFIG_HAS_ETH0 | |
| 726 | #define CONFIG_HAS_ETH1 | |
| 727 | #define CONFIG_HAS_ETH2 | |
| 728 | #endif /* CONFIG_TSEC_ENET */ | |
| 729 | ||
| 730 | #ifdef CONFIG_QE | |
| 731 | /* QE microcode/firmware address */ | |
| f2717b47 | 732 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| dcf1d774 | 733 | #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 |
| f2717b47 | 734 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 14aa71e6 LY |
735 | #endif /* CONFIG_QE */ |
| 736 | ||
| b0c98b4b | 737 | #ifdef CONFIG_TARGET_P1025RDB |
| 14aa71e6 LY |
738 | /* |
| 739 | * QE UEC ethernet configuration | |
| 740 | */ | |
| 741 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
| 742 | ||
| 743 | #undef CONFIG_UEC_ETH | |
| 744 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
| 745 | ||
| 746 | #define CONFIG_UEC_ETH1 /* ETH1 */ | |
| 747 | #define CONFIG_HAS_ETH0 | |
| 748 | ||
| 749 | #ifdef CONFIG_UEC_ETH1 | |
| 750 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
| 751 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ | |
| 752 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ | |
| 753 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
| 754 | #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ | |
| 755 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
| 756 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 | |
| 757 | #endif /* CONFIG_UEC_ETH1 */ | |
| 758 | ||
| 759 | #define CONFIG_UEC_ETH5 /* ETH5 */ | |
| 760 | #define CONFIG_HAS_ETH1 | |
| 761 | ||
| 762 | #ifdef CONFIG_UEC_ETH5 | |
| 763 | #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ | |
| 764 | #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE | |
| 765 | #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ | |
| 766 | #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH | |
| 767 | #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ | |
| 768 | #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
| 769 | #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 | |
| 770 | #endif /* CONFIG_UEC_ETH5 */ | |
| b0c98b4b | 771 | #endif /* CONFIG_TARGET_P1025RDB */ |
| 14aa71e6 LY |
772 | |
| 773 | /* | |
| 774 | * Environment | |
| 775 | */ | |
| d34e5624 | 776 | #ifdef CONFIG_SPIFLASH |
| 14aa71e6 LY |
777 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 778 | #define CONFIG_ENV_SPI_BUS 0 | |
| 779 | #define CONFIG_ENV_SPI_CS 0 | |
| 780 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 781 | #define CONFIG_ENV_SPI_MODE 0 | |
| 782 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 783 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 784 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 3e6e6983 | 785 | #elif defined(CONFIG_SDCARD) |
| 14aa71e6 | 786 | #define CONFIG_ENV_IS_IN_MMC |
| 4394d0c2 | 787 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 14aa71e6 LY |
788 | #define CONFIG_ENV_SIZE 0x2000 |
| 789 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| a796e72c | 790 | #elif defined(CONFIG_NAND) |
| 62c6ef33 YZ |
791 | #ifdef CONFIG_TPL_BUILD |
| 792 | #define CONFIG_ENV_SIZE 0x2000 | |
| 793 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
| 794 | #else | |
| 14aa71e6 | 795 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 62c6ef33 YZ |
796 | #endif |
| 797 | #define CONFIG_ENV_IS_IN_NAND | |
| 798 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
| 14aa71e6 | 799 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| a796e72c | 800 | #elif defined(CONFIG_SYS_RAMBOOT) |
| 14aa71e6 LY |
801 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| 802 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 803 | #define CONFIG_ENV_SIZE 0x2000 | |
| 14aa71e6 LY |
804 | #else |
| 805 | #define CONFIG_ENV_IS_IN_FLASH | |
| 14aa71e6 | 806 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 14aa71e6 LY |
807 | #define CONFIG_ENV_SIZE 0x2000 |
| 808 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 809 | #endif | |
| 810 | ||
| 811 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 812 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 813 | ||
| 814 | /* | |
| 815 | * Command line configuration. | |
| 816 | */ | |
| 14aa71e6 | 817 | #define CONFIG_CMD_IRQ |
| 14aa71e6 LY |
818 | #define CONFIG_CMD_REGINFO |
| 819 | ||
| 820 | /* | |
| 821 | * USB | |
| 822 | */ | |
| 823 | #define CONFIG_HAS_FSL_DR_USB | |
| 824 | ||
| 825 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 826 | #define CONFIG_USB_EHCI | |
| 827 | ||
| 828 | #ifdef CONFIG_USB_EHCI | |
| 14aa71e6 LY |
829 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 830 | #define CONFIG_USB_EHCI_FSL | |
| 14aa71e6 LY |
831 | #endif |
| 832 | #endif | |
| 833 | ||
| f404b66c | 834 | #if defined(CONFIG_TARGET_P1020RDB_PD) |
| 80ba6a6f | 835 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 836 | #endif | |
| 837 | ||
| 14aa71e6 LY |
838 | #ifdef CONFIG_MMC |
| 839 | #define CONFIG_FSL_ESDHC | |
| 840 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 14aa71e6 LY |
841 | #endif |
| 842 | ||
| 14aa71e6 LY |
843 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 844 | ||
| 845 | /* | |
| 846 | * Miscellaneous configurable options | |
| 847 | */ | |
| 848 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 849 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 850 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 14aa71e6 LY |
851 | #if defined(CONFIG_CMD_KGDB) |
| 852 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 853 | #else | |
| 854 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 855 | #endif | |
| 856 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 857 | /* Print Buffer Size */ | |
| 858 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 859 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 14aa71e6 LY |
860 | |
| 861 | /* | |
| 862 | * For booting Linux, the board info and command line data | |
| 863 | * have to be in the first 64 MB of memory, since this is | |
| 864 | * the maximum mapped by the Linux kernel during initialization. | |
| 865 | */ | |
| 866 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ | |
| 867 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 868 | ||
| 869 | #if defined(CONFIG_CMD_KGDB) | |
| 870 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 14aa71e6 LY |
871 | #endif |
| 872 | ||
| 873 | /* | |
| 874 | * Environment Configuration | |
| 875 | */ | |
| 876 | #define CONFIG_HOSTNAME unknown | |
| 8b3637c6 | 877 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 878 | #define CONFIG_BOOTFILE "uImage" |
| 14aa71e6 LY |
879 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 880 | ||
| 881 | /* default location for tftp and bootm */ | |
| 882 | #define CONFIG_LOADADDR 1000000 | |
| 883 | ||
| 14aa71e6 LY |
884 | #define CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 885 | ||
| 14aa71e6 LY |
886 | #ifdef __SW_BOOT_NOR |
| 887 | #define __NOR_RST_CMD \ | |
| 888 | norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ | |
| 889 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
| 890 | #endif | |
| 891 | #ifdef __SW_BOOT_SPI | |
| 892 | #define __SPI_RST_CMD \ | |
| 893 | spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ | |
| 894 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
| 895 | #endif | |
| 896 | #ifdef __SW_BOOT_SD | |
| 897 | #define __SD_RST_CMD \ | |
| 898 | sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ | |
| 899 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
| 900 | #endif | |
| 901 | #ifdef __SW_BOOT_NAND | |
| 902 | #define __NAND_RST_CMD \ | |
| 903 | nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ | |
| 904 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
| 905 | #endif | |
| 906 | #ifdef __SW_BOOT_PCIE | |
| 907 | #define __PCIE_RST_CMD \ | |
| 908 | pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ | |
| 909 | i2c mw 18 3 __SW_BOOT_MASK 1; reset | |
| 910 | #endif | |
| 911 | ||
| 912 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 913 | "netdev=eth0\0" \ | |
| 5368c55d | 914 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 14aa71e6 LY |
915 | "loadaddr=1000000\0" \ |
| 916 | "bootfile=uImage\0" \ | |
| 917 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 5368c55d MV |
918 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 919 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 920 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 921 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 922 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 14aa71e6 LY |
923 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
| 924 | "consoledev=ttyS0\0" \ | |
| 925 | "ramdiskaddr=2000000\0" \ | |
| 926 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 927 | "fdtaddr=1e00000\0" \ |
| 14aa71e6 LY |
928 | "bdev=sda1\0" \ |
| 929 | "jffs2nor=mtdblock3\0" \ | |
| 930 | "norbootaddr=ef080000\0" \ | |
| 931 | "norfdtaddr=ef040000\0" \ | |
| 932 | "jffs2nand=mtdblock9\0" \ | |
| 933 | "nandbootaddr=100000\0" \ | |
| 934 | "nandfdtaddr=80000\0" \ | |
| 935 | "ramdisk_size=120000\0" \ | |
| 936 | "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ | |
| 937 | "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ | |
| 5368c55d MV |
938 | __stringify(__NOR_RST_CMD)"\0" \ |
| 939 | __stringify(__SPI_RST_CMD)"\0" \ | |
| 940 | __stringify(__SD_RST_CMD)"\0" \ | |
| 941 | __stringify(__NAND_RST_CMD)"\0" \ | |
| 942 | __stringify(__PCIE_RST_CMD)"\0" | |
| 14aa71e6 LY |
943 | |
| 944 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 945 | "setenv bootargs root=/dev/nfs rw " \ | |
| 946 | "nfsroot=$serverip:$rootpath " \ | |
| 947 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 948 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 949 | "tftp $loadaddr $bootfile;" \ | |
| 950 | "tftp $fdtaddr $fdtfile;" \ | |
| 951 | "bootm $loadaddr - $fdtaddr" | |
| 952 | ||
| 953 | #define CONFIG_HDBOOT \ | |
| 954 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 955 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 956 | "usb start;" \ | |
| 957 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 958 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 959 | "bootm $loadaddr - $fdtaddr" | |
| 960 | ||
| 961 | #define CONFIG_USB_FAT_BOOT \ | |
| 962 | "setenv bootargs root=/dev/ram rw " \ | |
| 963 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 964 | "ramdisk_size=$ramdisk_size;" \ | |
| 965 | "usb start;" \ | |
| 966 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 967 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 968 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 969 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 970 | ||
| 971 | #define CONFIG_USB_EXT2_BOOT \ | |
| 972 | "setenv bootargs root=/dev/ram rw " \ | |
| 973 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 974 | "ramdisk_size=$ramdisk_size;" \ | |
| 975 | "usb start;" \ | |
| 976 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 977 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 978 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 979 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 980 | ||
| 981 | #define CONFIG_NORBOOT \ | |
| 982 | "setenv bootargs root=/dev/$jffs2nor rw " \ | |
| 983 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
| 984 | "bootm $norbootaddr - $norfdtaddr" | |
| 985 | ||
| 986 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 987 | "setenv bootargs root=/dev/ram rw " \ | |
| 988 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 989 | "ramdisk_size=$ramdisk_size;" \ | |
| 990 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 991 | "tftp $loadaddr $bootfile;" \ | |
| 992 | "tftp $fdtaddr $fdtfile;" \ | |
| 993 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 994 | ||
| 995 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 996 | ||
| 997 | #endif /* __CONFIG_H */ |