[people/ms/u-boot.git] / include / configs / p1_twr.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * QorIQ P1 Tower boards configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_PHY_ATHEROS
#define CONFIG_QE
#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
#define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0xeff40000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_MP

#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */

#define CONFIG_TSEC_ENET	/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_LIBATA
#define CONFIG_LBA48

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */

#define CONFIG_DDR_CLK_FREQ	66666666

#define CONFIG_HWCONFIG
/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x1fffffff
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */

#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

/* Default settings for DDR3 */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000

#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000

#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
#define CONFIG_SYS_DDR_RCW_1		0x00000000
#define CONFIG_SYS_DDR_RCW_2		0x00000000
#define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
#define CONFIG_SYS_DDR_TIMING_4		0x00220001
#define CONFIG_SYS_DDR_TIMING_5		0x03402400

#define CONFIG_SYS_DDR_TIMING_3		0x00020000
#define CONFIG_SYS_DDR_TIMING_0		0x00220004
#define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
#define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
#define CONFIG_SYS_DDR_MODE_1		0x80461320
#define CONFIG_SYS_DDR_MODE_2		0x00008000
#define CONFIG_SYS_DDR_INTERVAL		0x09480000

/*
 * Memory map
 *
 * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
 * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
 * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
 *
 * Localbus
 * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
 * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
 *
 * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
 * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
 * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
#define CONFIG_SYS_FLASH_BASE		0xec000000

#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	| BR_PS_16 | BR_V)

#define CONFIG_FLASH_OR_PRELIM	0xfc0000b1

#define CONFIG_SYS_SSD_BASE	0xe0000000
#define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
#define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
					BR_PS_16 | BR_V)
#define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)

#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
/* Size of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */

/* Serial Port
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX		1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52

/*
 * I2C2 EEPROM
 */
#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_SYS_I2C_PCA9555_ADDR	0x23

/* enable read and write access to EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_HARD_SPI

#if defined(CONFIG_PCI)
/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#define CONFIG_CMD_PCI

#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		/* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#undef CONFIG_TSEC2
#undef CONFIG_TSEC2_NAME
#define CONFIG_TSEC3
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define TSEC1_PHY_ADDR	2
#define TSEC2_PHY_ADDR	0
#define TSEC3_PHY_ADDR	1

#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX	0
#define TSEC2_PHYIDX	0
#define TSEC3_PHYIDX	0

#define CONFIG_ETHPRIME	"eTSEC1"

#define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#undef CONFIG_HAS_ETH2
#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#endif /* CONFIG_QE */

#ifdef CONFIG_TWR_P1025
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)

#undef CONFIG_UEC_ETH
#define CONFIG_PHY_MODE_NEED_CHANGE

#define CONFIG_UEC_ETH1	/* ETH1 */
#define CONFIG_HAS_ETH0

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH1 */

#define CONFIG_UEC_ETH5	/* ETH5 */
#define CONFIG_HAS_ETH1

#ifdef CONFIG_UEC_ETH5
#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH5 */
#endif /* CONFIG_TWR-P1025 */

/*
 * Dynamic MTD Partition support with mtdparts
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
			"256k(dtb),5632k(kernel),57856k(fs)," \
			"256k(qe-ucode-firmware),1280k(u-boot)"

/*
 * Environment
 */
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SDCARD
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_SYS_MMC_ENV_DEV	0
#else
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Command line configuration.
 */
#define CONFIG_CMD_REGINFO

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB

#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#endif

#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

#undef CONFIG_WATCHDOG	/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR	1000000

#define CONFIG_BOOTARGS	/* the boot command will set bootargs */

#define	CONFIG_EXTRA_ENV_SETTINGS	\
"netdev=eth0\0"	\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
"loadaddr=1000000\0"	\
"bootfile=uImage\0"	\
"dtbfile=twr-p1025twr.dtb\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
"tftpflash=tftpboot $loadaddr $uboot; "	\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"kernelflash=tftpboot $loadaddr $bootfile; "	\
	"protect off 0xefa80000 +$filesize; "	\
	"erase 0xefa80000 +$filesize; "	\
	"cp.b $loadaddr 0xefa80000 $filesize; "	\
	"protect on 0xefa80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
"dtbflash=tftpboot $loadaddr $dtbfile; "	\
	"protect off 0xefe80000 +$filesize; "	\
	"erase 0xefe80000 +$filesize; "	\
	"cp.b $loadaddr 0xefe80000 $filesize; "	\
	"protect on 0xefe80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
	"protect off 0xeeb80000 +$filesize; "	\
	"erase 0xeeb80000 +$filesize; "	\
	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
	"protect on 0xeeb80000 +$filesize; "	\
	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
	"protect off 0xefec0000 +$filesize; "	\
	"erase 0xefec0000 +$filesize; "	\
	"cp.b $loadaddr 0xefec0000 $filesize; "	\
	"protect on 0xefec0000 +$filesize; "	\
	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
"consoledev=ttyS0\0"	\
"ramdiskaddr=2000000\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"fdtaddr=1e00000\0"	\
"bdev=sda1\0"	\
"norbootaddr=ef080000\0"	\
"norfdtaddr=ef040000\0"	\
"ramdisk_size=120000\0" \
"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"

#define CONFIG_NFSBOOTCOMMAND	\
"setenv bootargs root=/dev/nfs rw "	\
"nfsroot=$serverip:$rootpath "	\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile&&"	\
"tftp $fdtaddr $fdtfile&&"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_HDBOOT	\
"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;"	\
"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_USB_FAT_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"fatload usb 0:2 $loadaddr $bootfile;"	\
"fatload usb 0:2 $fdtaddr $fdtfile;"	\
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_USB_EXT2_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"ext2load usb 0:4 $loadaddr $bootfile;"	\
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_NORBOOT	\
"setenv bootargs root=/dev/mtdblock3 rw "	\
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
"bootm $norbootaddr - $norfdtaddr"

#define CONFIG_RAMBOOTCOMMAND_TFTP	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"tftp $ramdiskaddr $ramdiskfile;"	\
"tftp $loadaddr $bootfile;"	\
"tftp $fdtaddr $fdtfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"bootm 0xefa80000 0xeeb80000 0xefe80000"

#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND

#endif /* __CONFIG_H */
Commit	Line	Data
49f5befa XX	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
3aab0cd8	4	* SPDX-License-Identifier: GPL-2.0+
49f5befa XX	5	*/
	6
	7	/*
	8	* QorIQ P1 Tower boards configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#if defined(CONFIG_TWR_P1025)
	14	#define CONFIG_BOARDNAME "TWR-P1025"
49f5befa XX	15	#define CONFIG_PHY_ATHEROS
	16	#define CONFIG_QE
	17	#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
	18	#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
	19	#endif
	20
	21	#ifdef CONFIG_SDCARD
	22	#define CONFIG_RAMBOOT_SDCARD
	23	#define CONFIG_SYS_RAMBOOT
	24	#define CONFIG_SYS_EXTRA_ENV_RELOC
	25	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	26	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
49f5befa XX	27	#endif
	28
	29	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	30	#define CONFIG_SYS_TEXT_BASE 0xeff40000
49f5befa XX	31	#endif
	32
	33	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	34	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	35	#endif
	36
	37	#ifndef CONFIG_SYS_MONITOR_BASE
	38	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	39	#endif
	40
49f5befa XX	41	#define CONFIG_MP
49f5befa XX	42
b38eaec5 RD	43	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b38eaec5 RD	44	#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
49f5befa XX	45	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	46	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
	47	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	48	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	49
49f5befa XX	50	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	51	#define CONFIG_ENV_OVERWRITE
	52
49f5befa XX	53	#define CONFIG_SATA_SIL3114
	54	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	55	#define CONFIG_LIBATA
	56	#define CONFIG_LBA48
	57
	58	#ifndef __ASSEMBLY__
	59	extern unsigned long get_board_sys_clk(unsigned long dummy);
	60	#endif
	61	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /sysclk for TWR-P1025 /
	62
	63	#define CONFIG_DDR_CLK_FREQ 66666666
	64
	65	#define CONFIG_HWCONFIG
	66	/*
	67	* These can be toggled for performance analysis, otherwise use default.
	68	*/
	69	#define CONFIG_L2_CACHE
	70	#define CONFIG_BTB
	71
49f5befa XX	72	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	73	#define CONFIG_SYS_MEMTEST_END 0x1fffffff
	74	#define CONFIG_PANIC_HANG /* do not reset board on panic */
	75
	76	#define CONFIG_SYS_CCSRBAR 0xffe00000
	77	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	78
	79	/* DDR Setup */
49f5befa XX	80
	81	#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
	82	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	83
	84	#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
	85	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	86	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	87
49f5befa XX	88	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	89
	90	/* Default settings for DDR3 */
	91	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
	92	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
	93	#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
	94	#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
	95	#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
	96	#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
	97
	98	#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
	99	#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
	100	#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
	101	#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
	102
	103	#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
	104	#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
	105	#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
	106	#define CONFIG_SYS_DDR_RCW_1 0x00000000
	107	#define CONFIG_SYS_DDR_RCW_2 0x00000000
	108	#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
	109	#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
	110	#define CONFIG_SYS_DDR_TIMING_4 0x00220001
	111	#define CONFIG_SYS_DDR_TIMING_5 0x03402400
	112
	113	#define CONFIG_SYS_DDR_TIMING_3 0x00020000
	114	#define CONFIG_SYS_DDR_TIMING_0 0x00220004
	115	#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
	116	#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
	117	#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
	118	#define CONFIG_SYS_DDR_MODE_1 0x80461320
	119	#define CONFIG_SYS_DDR_MODE_2 0x00008000
	120	#define CONFIG_SYS_DDR_INTERVAL 0x09480000
	121
	122	/*
	123	* Memory map
	124	*
	125	* 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
	126	* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
	127	* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
	128	*
	129	* Localbus
	130	* 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
	131	* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
	132	*
	133	* 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
	134	* 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
	135	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	136	*/
	137
	138	/*
	139	* Local Bus Definitions
	140	*/
	141	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	142	#define CONFIG_SYS_FLASH_BASE 0xec000000
	143
	144	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	145
	146	#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	147	\| BR_PS_16 \| BR_V)
	148
	149	#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
	150
	151	#define CONFIG_SYS_SSD_BASE 0xe0000000
152	#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
153	#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) \| \
154	BR_PS_16 \| BR_V)
155	#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB \| OR_GPCM_CSNT \| OR_GPCM_XACS \| \
156	OR_GPCM_ACS_DIV2 \| OR_GPCM_SCY \| \
157	OR_GPCM_TRLX \| OR_GPCM_EHTR \| OR_GPCM_EAD)
158
159	#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
160	#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
161
162	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
163	#define CONFIG_SYS_FLASH_QUIET_TEST
164	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
165
166	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
167
168	#undef CONFIG_SYS_FLASH_CHECKSUM
169	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
170	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
171
172	#define CONFIG_FLASH_CFI_DRIVER
173	#define CONFIG_SYS_FLASH_CFI
174	#define CONFIG_SYS_FLASH_EMPTY_INFO
175	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
176
177	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
178
179	#define CONFIG_SYS_INIT_RAM_LOCK
180	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
181	/* Initial L1 address */
182	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
183	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
184	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
185	/* Size of used area in RAM */
186	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
187
188	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
189	GENERATED_GBL_DATA_SIZE)
190	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
191
9307cbab	192	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
49f5befa XX	193	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
	194
	195	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	196	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	197
	198	/* Serial Port
	199	* open - index 2
	200	* shorted - index 1
	201	*/
	202	#define CONFIG_CONS_INDEX 1
	203	#undef CONFIG_SERIAL_SOFTWARE_FIFO
49f5befa XX	204	#define CONFIG_SYS_NS16550_SERIAL
	205	#define CONFIG_SYS_NS16550_REG_SIZE 1
	206	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	207
	208	#define CONFIG_SYS_BAUDRATE_TABLE \
	209	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	210
	211	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	212	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	213
49f5befa XX	214	/* I2C */
	215	#define CONFIG_SYS_I2C
	216	#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
	217	#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
	218	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	219	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	220	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	221
	222	/*
	223	* I2C2 EEPROM
	224	*/
	225	#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
	226	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	227	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	228
	229	#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
	230
	231	/* enable read and write access to EEPROM */
49f5befa XX	232	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	233	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	234	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	235
	236	/*
	237	* eSPI - Enhanced SPI
	238	*/
	239	#define CONFIG_HARD_SPI
49f5befa XX	240
	241	#if defined(CONFIG_PCI)
	242	/*
	243	* General PCI
	244	* Memory space is mapped 1-1, but I/O space must start from 0.
	245	*/
	246
	247	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	248	#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
	249	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	250	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	251	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	252	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	253	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	254	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	255	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	256	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	257
	258	/* controller 1, tgtid 1, Base address a000 */
	259	#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
	260	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	261	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	262	#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
	263	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	264	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	265	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	266	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
	267	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	268
49f5befa	269	#define CONFIG_CMD_PCI
49f5befa XX	270
49f5befa XX	271	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
49f5befa XX	272	#endif /* CONFIG_PCI */
	273
	274	#if defined(CONFIG_TSEC_ENET)
	275
49f5befa XX	276	#define CONFIG_MII /* MII PHY management */
	277	#define CONFIG_TSEC1
	278	#define CONFIG_TSEC1_NAME "eTSEC1"
	279	#undef CONFIG_TSEC2
	280	#undef CONFIG_TSEC2_NAME
	281	#define CONFIG_TSEC3
	282	#define CONFIG_TSEC3_NAME "eTSEC3"
	283
	284	#define TSEC1_PHY_ADDR 2
	285	#define TSEC2_PHY_ADDR 0
	286	#define TSEC3_PHY_ADDR 1
	287
	288	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	289	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	290	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	291
	292	#define TSEC1_PHYIDX 0
	293	#define TSEC2_PHYIDX 0
	294	#define TSEC3_PHYIDX 0
	295
	296	#define CONFIG_ETHPRIME "eTSEC1"
	297
	298	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	299
	300	#define CONFIG_HAS_ETH0
	301	#define CONFIG_HAS_ETH1
	302	#undef CONFIG_HAS_ETH2
	303	#endif /* CONFIG_TSEC_ENET */
	304
	305	#ifdef CONFIG_QE
	306	/* QE microcode/firmware address */
	307	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
dcf1d774	308	#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
49f5befa XX	309	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	310	#endif /* CONFIG_QE */
	311
	312	#ifdef CONFIG_TWR_P1025
	313	/*
	314	* QE UEC ethernet configuration
	315	*/
	316	#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
	317
	318	#undef CONFIG_UEC_ETH
	319	#define CONFIG_PHY_MODE_NEED_CHANGE
	320
	321	#define CONFIG_UEC_ETH1 /* ETH1 */
	322	#define CONFIG_HAS_ETH0
	323
	324	#ifdef CONFIG_UEC_ETH1
	325	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	326	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
	327	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
	328	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	329	#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
	330	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
	331	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	332	#endif /* CONFIG_UEC_ETH1 */
	333
	334	#define CONFIG_UEC_ETH5 /* ETH5 */
	335	#define CONFIG_HAS_ETH1
	336
	337	#ifdef CONFIG_UEC_ETH5
	338	#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
	339	#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
	340	#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
	341	#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
	342	#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
	343	#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	344	#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
	345	#endif /* CONFIG_UEC_ETH5 */
	346	#endif /* CONFIG_TWR-P1025 */
	347
94b383e7 YL	348	/*
	349	* Dynamic MTD Partition support with mtdparts
	350	*/
	351	#define CONFIG_MTD_DEVICE
	352	#define CONFIG_MTD_PARTITIONS
94b383e7 YL	353	#define CONFIG_FLASH_CFI_MTD
	354	#define MTDIDS_DEFAULT "nor0=ec000000.nor"
	355	#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
	356	"256k(dtb),5632k(kernel),57856k(fs)," \
	357	"256k(qe-ucode-firmware),1280k(u-boot)"
	358
49f5befa XX	359	/*
	360	* Environment
	361	*/
	362	#ifdef CONFIG_SYS_RAMBOOT
	363	#ifdef CONFIG_RAMBOOT_SDCARD
49f5befa XX	364	#define CONFIG_ENV_SIZE 0x2000
	365	#define CONFIG_SYS_MMC_ENV_DEV 0
	366	#else
49f5befa XX	367	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	368	#define CONFIG_ENV_SIZE 0x2000
	369	#endif
	370	#else
	371	#define CONFIG_ENV_IS_IN_FLASH
49f5befa	372	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
49f5befa XX	373	#define CONFIG_ENV_SIZE 0x2000
	374	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
	375	#endif
	376
	377	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	378	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	379
	380	/*
	381	* Command line configuration.
	382	*/
49f5befa XX	383	#define CONFIG_CMD_REGINFO
	384
	385	/*
	386	* USB
	387	*/
	388	#define CONFIG_HAS_FSL_DR_USB
	389
	390	#if defined(CONFIG_HAS_FSL_DR_USB)
8850c5d5	391	#ifdef CONFIG_USB_EHCI_HCD
49f5befa XX	392	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
49f5befa XX	393	#define CONFIG_USB_EHCI_FSL
49f5befa XX	394	#endif
	395	#endif
	396
49f5befa XX	397	#ifdef CONFIG_MMC
	398	#define CONFIG_FSL_ESDHC
	399	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
49f5befa XX	400	#endif
49f5befa XX	401
49f5befa XX	402	#undef CONFIG_WATCHDOG /* watchdog disabled */
	403
	404	/*
	405	* Miscellaneous configurable options
	406	*/
	407	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	408	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	409	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
49f5befa XX	410	#if defined(CONFIG_CMD_KGDB)
	411	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	412	#else
	413	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	414	#endif
	415	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	416	/* Print Buffer Size */
	417	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	418	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
49f5befa XX	419
	420	/*
	421	* For booting Linux, the board info and command line data
	422	* have to be in the first 64 MB of memory, since this is
	423	* the maximum mapped by the Linux kernel during initialization.
	424	*/
	425	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
	426	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	427
	428	/*
	429	* Environment Configuration
	430	*/
	431	#define CONFIG_HOSTNAME unknown
	432	#define CONFIG_ROOTPATH "/opt/nfsroot"
	433	#define CONFIG_BOOTFILE "uImage"
	434	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
	435
	436	/* default location for tftp and bootm */
	437	#define CONFIG_LOADADDR 1000000
	438
49f5befa XX	439	#define CONFIG_BOOTARGS /* the boot command will set bootargs */
49f5befa XX	440
49f5befa XX	441	#define CONFIG_EXTRA_ENV_SETTINGS \
	442	"netdev=eth0\0" \
	443	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	444	"loadaddr=1000000\0" \
	445	"bootfile=uImage\0" \
	446	"dtbfile=twr-p1025twr.dtb\0" \
	447	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	448	"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
	449	"tftpflash=tftpboot $loadaddr $uboot; " \
	450	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	451	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	452	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	453	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	454	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
	455	"kernelflash=tftpboot $loadaddr $bootfile; " \
	456	"protect off 0xefa80000 +$filesize; " \
	457	"erase 0xefa80000 +$filesize; " \
	458	"cp.b $loadaddr 0xefa80000 $filesize; " \
	459	"protect on 0xefa80000 +$filesize; " \
	460	"cmp.b $loadaddr 0xefa80000 $filesize\0" \
	461	"dtbflash=tftpboot $loadaddr $dtbfile; " \
	462	"protect off 0xefe80000 +$filesize; " \
	463	"erase 0xefe80000 +$filesize; " \
	464	"cp.b $loadaddr 0xefe80000 $filesize; " \
	465	"protect on 0xefe80000 +$filesize; " \
	466	"cmp.b $loadaddr 0xefe80000 $filesize\0" \
	467	"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
	468	"protect off 0xeeb80000 +$filesize; " \
	469	"erase 0xeeb80000 +$filesize; " \
	470	"cp.b $loadaddr 0xeeb80000 $filesize; " \
	471	"protect on 0xeeb80000 +$filesize; " \
	472	"cmp.b $loadaddr 0xeeb80000 $filesize\0" \
	473	"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
	474	"protect off 0xefec0000 +$filesize; " \
	475	"erase 0xefec0000 +$filesize; " \
	476	"cp.b $loadaddr 0xefec0000 $filesize; " \
	477	"protect on 0xefec0000 +$filesize; " \
	478	"cmp.b $loadaddr 0xefec0000 $filesize\0" \
	479	"consoledev=ttyS0\0" \
	480	"ramdiskaddr=2000000\0" \
	481	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	482	"fdtaddr=1e00000\0" \
49f5befa XX	483	"bdev=sda1\0" \
	484	"norbootaddr=ef080000\0" \
	485	"norfdtaddr=ef040000\0" \
	486	"ramdisk_size=120000\0" \
	487	"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
	488	"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
	489
	490	#define CONFIG_NFSBOOTCOMMAND \
	491	"setenv bootargs root=/dev/nfs rw " \
	492	"nfsroot=$serverip:$rootpath " \
	493	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	494	"console=$consoledev,$baudrate $othbootargs;" \
	495	"tftp $loadaddr $bootfile&&" \
	496	"tftp $fdtaddr $fdtfile&&" \
	497	"bootm $loadaddr - $fdtaddr"
	498
	499	#define CONFIG_HDBOOT \
	500	"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
	501	"console=$consoledev,$baudrate $othbootargs;" \
	502	"usb start;" \
	503	"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
	504	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
	505	"bootm $loadaddr - $fdtaddr"
	506
	507	#define CONFIG_USB_FAT_BOOT \
	508	"setenv bootargs root=/dev/ram rw " \
	509	"console=$consoledev,$baudrate $othbootargs " \
	510	"ramdisk_size=$ramdisk_size;" \
	511	"usb start;" \
	512	"fatload usb 0:2 $loadaddr $bootfile;" \
	513	"fatload usb 0:2 $fdtaddr $fdtfile;" \
	514	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
	515	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	516
	517	#define CONFIG_USB_EXT2_BOOT \
	518	"setenv bootargs root=/dev/ram rw " \
	519	"console=$consoledev,$baudrate $othbootargs " \
	520	"ramdisk_size=$ramdisk_size;" \
	521	"usb start;" \
	522	"ext2load usb 0:4 $loadaddr $bootfile;" \
	523	"ext2load usb 0:4 $fdtaddr $fdtfile;" \
	524	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
	525	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	526
	527	#define CONFIG_NORBOOT \
	528	"setenv bootargs root=/dev/mtdblock3 rw " \
	529	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
	530	"bootm $norbootaddr - $norfdtaddr"
	531
	532	#define CONFIG_RAMBOOTCOMMAND_TFTP \
	533	"setenv bootargs root=/dev/ram rw " \
	534	"console=$consoledev,$baudrate $othbootargs " \
	535	"ramdisk_size=$ramdisk_size;" \
	536	"tftp $ramdiskaddr $ramdiskfile;" \
	537	"tftp $loadaddr $bootfile;" \
	538	"tftp $fdtaddr $fdtfile;" \
	539	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	540
	541	#define CONFIG_RAMBOOTCOMMAND \
	542	"setenv bootargs root=/dev/ram rw " \
	543	"console=$consoledev,$baudrate $othbootargs " \
	544	"ramdisk_size=$ramdisk_size;" \
	545	"bootm 0xefa80000 0xeeb80000 0xefe80000"
	546
547	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
548
549	#endif /* __CONFIG_H */