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10a03382 SW |
1 | /* |
2 | * Copyright (c) 2013-2016, NVIDIA CORPORATION. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #ifndef _P2771_0000_H | |
8 | #define _P2771_0000_H | |
9 | ||
10 | #include <linux/sizes.h> | |
11 | ||
12 | #include "tegra186-common.h" | |
13 | ||
14 | /* High-level configuration options */ | |
15 | #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" | |
16 | ||
ad3c144f BW |
17 | /* I2C */ |
18 | #define CONFIG_SYS_I2C_TEGRA | |
19 | ||
10a03382 | 20 | /* Environment in eMMC, at the end of 2nd "boot sector" */ |
10a03382 SW |
21 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
22 | #define CONFIG_SYS_MMC_ENV_PART 2 | |
23 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) | |
24 | ||
a6bb0084 | 25 | /* PCI host support */ |
a6bb0084 | 26 | |
e43effc1 SW |
27 | #define BOARD_EXTRA_ENV_SETTINGS \ |
28 | "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ | |
29 | "ramdisk_addr_r\0" \ | |
30 | "kernel_addr_r_align=00200000\0" \ | |
31 | "kernel_addr_r_offset=00080000\0" \ | |
32 | "kernel_addr_r_size=02000000\0" \ | |
33 | "kernel_addr_r_aliases=loadaddr\0" \ | |
34 | "fdt_addr_r_align=00200000\0" \ | |
35 | "fdt_addr_r_offset=00000000\0" \ | |
36 | "fdt_addr_r_size=00200000\0" \ | |
37 | "scriptaddr_align=00200000\0" \ | |
38 | "scriptaddr_offset=00000000\0" \ | |
39 | "scriptaddr_size=00200000\0" \ | |
40 | "pxefile_addr_r_align=00200000\0" \ | |
41 | "pxefile_addr_r_offset=00000000\0" \ | |
42 | "pxefile_addr_r_size=00200000\0" \ | |
43 | "ramdisk_addr_r_align=00200000\0" \ | |
44 | "ramdisk_addr_r_offset=00000000\0" \ | |
45 | "ramdisk_addr_r_size=02000000\0" | |
46 | ||
10a03382 SW |
47 | #include "tegra-common-post.h" |
48 | ||
49 | /* Crystal is 38.4MHz. clk_m runs at half that rate */ | |
50 | #define COUNTER_FREQUENCY 19200000 | |
51 | ||
a9819b9e SW |
52 | #undef CONFIG_NR_DRAM_BANKS |
53 | #define CONFIG_NR_DRAM_BANKS (1024 + 2) | |
54 | ||
10a03382 | 55 | #endif |