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10a03382 SW |
1 | /* |
2 | * Copyright (c) 2013-2016, NVIDIA CORPORATION. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #ifndef _P2771_0000_H | |
8 | #define _P2771_0000_H | |
9 | ||
10 | #include <linux/sizes.h> | |
11 | ||
12 | #include "tegra186-common.h" | |
13 | ||
14 | /* High-level configuration options */ | |
15 | #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" | |
16 | ||
ad3c144f BW |
17 | /* I2C */ |
18 | #define CONFIG_SYS_I2C_TEGRA | |
19 | ||
10a03382 SW |
20 | /* Environment in eMMC, at the end of 2nd "boot sector" */ |
21 | #define CONFIG_ENV_IS_IN_MMC | |
22 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
23 | #define CONFIG_SYS_MMC_ENV_PART 2 | |
24 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) | |
25 | ||
a6bb0084 | 26 | /* PCI host support */ |
a6bb0084 SW |
27 | #define CONFIG_CMD_PCI |
28 | ||
10a03382 SW |
29 | #include "tegra-common-post.h" |
30 | ||
31 | /* Crystal is 38.4MHz. clk_m runs at half that rate */ | |
32 | #define COUNTER_FREQUENCY 19200000 | |
33 | ||
34 | #endif |