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aaa2a2fc MV |
1 | /* |
2 | * Palm Tungsten|C configuration file | |
3 | * | |
4 | * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
aaa2a2fc MV |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include <asm/arch/pxa-regs.h> | |
13 | ||
14 | /* | |
15 | * High Level Board Configuration Options | |
16 | */ | |
abc20aba | 17 | #define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */ |
aaa2a2fc MV |
18 | #define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ |
19 | ||
89959081 SG |
20 | /* we will never enable dcache, because we have to setup MMU first */ |
21 | #define CONFIG_SYS_DCACHE_OFF | |
22 | ||
aaa2a2fc MV |
23 | /* |
24 | * Environment settings | |
25 | */ | |
26 | #define CONFIG_ENV_OVERWRITE | |
27 | #define CONFIG_SYS_MALLOC_LEN (128*1024) | |
0f7c54fb | 28 | #define CONFIG_SYS_TEXT_BASE 0x0 |
aaa2a2fc MV |
29 | |
30 | #define CONFIG_BOOTCOMMAND \ | |
31 | "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ | |
32 | "source 0xa0000000; " \ | |
33 | "else " \ | |
34 | "bootm 0x80000; " \ | |
35 | "fi; " | |
36 | #define CONFIG_BOOTARGS \ | |
37 | "console=tty0 console=ttyS0,115200" | |
38 | #define CONFIG_TIMESTAMP | |
39 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ | |
40 | #define CONFIG_CMDLINE_TAG | |
41 | #define CONFIG_SETUP_MEMORY_TAGS | |
42 | ||
43 | #define CONFIG_LZMA /* LZMA compression support */ | |
44 | ||
45 | /* | |
46 | * Serial Console Configuration | |
47 | * STUART - the lower serial port on Colibri board | |
48 | */ | |
49 | #define CONFIG_PXA_SERIAL | |
50 | #define CONFIG_FFUART 1 | |
ce6971cd | 51 | #define CONFIG_CONS_INDEX 3 |
aaa2a2fc | 52 | #define CONFIG_BAUDRATE 115200 |
aaa2a2fc MV |
53 | |
54 | /* | |
55 | * Bootloader Components Configuration | |
56 | */ | |
aaa2a2fc MV |
57 | #define CONFIG_CMD_ENV |
58 | #define CONFIG_CMD_MMC | |
59 | #define CONFIG_LCD | |
0698095a | 60 | #define CONFIG_PXA_LCD |
aaa2a2fc MV |
61 | |
62 | /* | |
63 | * MMC Card Configuration | |
64 | */ | |
65 | #ifdef CONFIG_CMD_MMC | |
66 | #define CONFIG_MMC | |
831f849f MV |
67 | #define CONFIG_GENERIC_MMC |
68 | #define CONFIG_PXA_MMC_GENERIC | |
aaa2a2fc MV |
69 | #define CONFIG_SYS_MMC_BASE 0xF0000000 |
70 | #define CONFIG_CMD_FAT | |
71 | #define CONFIG_CMD_EXT2 | |
72 | #define CONFIG_DOS_PARTITION | |
73 | #endif | |
74 | ||
75 | /* | |
76 | * LCD | |
77 | */ | |
78 | #ifdef CONFIG_LCD | |
79 | #define CONFIG_ACX517AKN | |
80 | #define CONFIG_VIDEO_LOGO | |
81 | #define CONFIG_CMD_BMP | |
82 | #define CONFIG_SPLASH_SCREEN | |
83 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
84 | #define CONFIG_VIDEO_BMP_GZIP | |
85 | #define CONFIG_VIDEO_BMP_RLE8 | |
86 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) | |
87 | #endif | |
88 | ||
89 | /* | |
90 | * KGDB | |
91 | */ | |
92 | #ifdef CONFIG_CMD_KGDB | |
93 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ | |
aaa2a2fc MV |
94 | #endif |
95 | ||
96 | /* | |
97 | * HUSH Shell Configuration | |
98 | */ | |
99 | #define CONFIG_SYS_HUSH_PARSER 1 | |
aaa2a2fc MV |
100 | |
101 | #define CONFIG_SYS_LONGHELP | |
102 | #ifdef CONFIG_SYS_HUSH_PARSER | |
103 | #define CONFIG_SYS_PROMPT "$ " | |
aaa2a2fc MV |
104 | #endif |
105 | #define CONFIG_SYS_CBSIZE 256 | |
106 | #define CONFIG_SYS_PBSIZE \ | |
107 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
108 | #define CONFIG_SYS_MAXARGS 16 | |
109 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
110 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
111 | ||
112 | /* | |
113 | * Clock Configuration | |
114 | */ | |
aaa2a2fc MV |
115 | #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ |
116 | ||
aaa2a2fc MV |
117 | /* |
118 | * DRAM Map | |
119 | */ | |
120 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ | |
121 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
122 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
123 | ||
124 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | |
125 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ | |
126 | ||
127 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | |
128 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
129 | ||
130 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE | |
131 | ||
6ef6eb91 | 132 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
00d5ec93 | 133 | #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 |
6ef6eb91 | 134 | |
aaa2a2fc MV |
135 | /* |
136 | * NOR FLASH | |
137 | */ | |
138 | #ifdef CONFIG_CMD_FLASH | |
139 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
140 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | |
141 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
142 | ||
143 | #define CONFIG_SYS_FLASH_CFI | |
144 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
145 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT | |
146 | ||
147 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
148 | #define CONFIG_SYS_MAX_FLASH_SECT 64 | |
149 | ||
150 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
151 | ||
f90aea2a MV |
152 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 |
153 | #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 | |
154 | #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 | |
155 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 | |
aaa2a2fc MV |
156 | #define CONFIG_SYS_FLASH_PROTECTION |
157 | ||
158 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
159 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
160 | #else | |
161 | #define CONFIG_SYS_NO_FLASH | |
162 | #define CONFIG_ENV_IS_NOWHERE | |
163 | #endif | |
164 | ||
165 | #define CONFIG_SYS_MONITOR_BASE 0x0 | |
166 | #define CONFIG_SYS_MONITOR_LEN 0x40000 | |
167 | ||
168 | #define CONFIG_ENV_SIZE 0x4000 | |
169 | #define CONFIG_ENV_ADDR 0x40000 | |
170 | ||
171 | /* | |
172 | * GPIO settings | |
173 | */ | |
174 | #define CONFIG_SYS_GAFR0_L_VAL 0x00011004 | |
175 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 | |
176 | #define CONFIG_SYS_GAFR1_L_VAL 0x60888050 | |
177 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa | |
178 | #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa | |
179 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 | |
180 | #define CONFIG_SYS_GPCR0_VAL 0x0 | |
181 | #define CONFIG_SYS_GPCR1_VAL 0x0 | |
182 | #define CONFIG_SYS_GPCR2_VAL 0x0 | |
183 | #define CONFIG_SYS_GPDR0_VAL 0xcfff8140 | |
184 | #define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 | |
185 | #define CONFIG_SYS_GPDR2_VAL 0x0001ffff | |
186 | #define CONFIG_SYS_GPSR0_VAL 0x00010f8f | |
187 | #define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 | |
188 | #define CONFIG_SYS_GPSR2_VAL 0x03fe0800 | |
189 | ||
190 | #define CONFIG_SYS_PSSR_VAL PSSR_RDH | |
191 | ||
192 | /* Clock setup: | |
193 | * CKEN[1] - PWM1 ; CKEN[6] - FFUART | |
194 | * CKEN[12] - MMC ; CKEN[16] - LCD | |
195 | */ | |
196 | #define CONFIG_SYS_CKEN 0x00011042 | |
197 | #define CONFIG_SYS_CCCR 0x00000161 | |
198 | ||
199 | /* | |
200 | * Memory settings | |
201 | */ | |
202 | #define CONFIG_SYS_MSC0_VAL 0x800092c2 | |
203 | #define CONFIG_SYS_MSC1_VAL 0x80008000 | |
204 | #define CONFIG_SYS_MSC2_VAL 0x80008000 | |
205 | #define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 | |
206 | #define CONFIG_SYS_MDREFR_VAL 0x00118018 | |
207 | #define CONFIG_SYS_MDMRS_VAL 0x00220032 | |
208 | #define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe | |
209 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | |
210 | ||
211 | /* | |
212 | * PCMCIA and CF Interfaces | |
213 | */ | |
214 | #define CONFIG_SYS_MECR_VAL 0x00000000 | |
215 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 | |
216 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 | |
217 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 | |
218 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 | |
219 | #define CONFIG_SYS_MCIO0_VAL 0x00010e04 | |
220 | #define CONFIG_SYS_MCIO1_VAL 0x00010e04 | |
221 | ||
222 | #endif /* __CONFIG_H */ |