[people/ms/u-boot.git] / include / configs / pcm052.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the phytec PCM-052 SoM.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

#define CONFIG_SKIP_LOWLEVEL_INIT

/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION

#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR

#define CONFIG_JFFS2_NAND

/* Dynamic MTD partition support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE

#endif

#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/

#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RMII
#define CONFIG_FEC_MXC_PHYADDR          0

/* QSPI Configs*/

#ifdef CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2
#define CONFIG_SYS_FSL_QSPI_LE
#endif

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC

/* RTC (actually an RV-4162 but M41T62-compatible) */
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_RTC_BUS_NUM 2

/* EEPROM (24FC256) */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_BUS 2


#define CONFIG_LOADADDR			0x82000000

/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_BOARD_SIZE_LIMIT		520192

/* if no target-specific extra environment settings were defined by the
   target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS
#define PCM052_EXTRA_ENV_SETTINGS
#endif

/* if no target-specific boot command was defined by the target,
   define an empty one */
#ifndef PCM052_BOOTCOMMAND
#define PCM052_BOOTCOMMAND
#endif

/* if no target-specific extra environment settings were defined by the
   target, define an empty one */
#ifndef PCM052_NET_INIT
#define PCM052_NET_INIT
#endif

/* boot command, including the target-defined one if any */
#define CONFIG_BOOTCOMMAND	PCM052_BOOTCOMMAND "run bootcmd_nand"

/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
	PCM052_EXTRA_ENV_SETTINGS \
	"autoload=no\0" \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"blimg_file=u-boot.vyb\0" \
	"blimg_addr=0x81000000\0" \
	"kernel_file=zImage\0" \
	"kernel_addr=0x82000000\0" \
	"fdt_file=zImage.dtb\0" \
	"fdt_addr=0x81000000\0" \
	"ram_file=uRamdisk\0" \
	"ram_addr=0x83000000\0" \
	"filesys=rootfs.ubifs\0" \
	"sys_addr=0x81000000\0" \
	"tftploc=/path/to/tftp/directory/\0" \
	"nfs_root=/path/to/nfs/root\0" \
	"tftptimeout=1000\0" \
	"tftptimeoutcountmax=1000000\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"bootargs_base=setenv bootargs rw " \
		" mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
		"console=ttyLP1,115200n8\0" \
	"bootargs_sd=setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 rootwait\0" \
	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
		"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
	"bootargs_nand=setenv bootargs ${bootargs} " \
		"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
	"bootargs_ram=setenv bootargs ${bootargs} " \
		"root=/dev/ram rw initrd=${ram_addr}\0" \
	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
		"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
		"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
		"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
		"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"nand read ${ram_addr} root; " \
		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
	"update_bootloader_from_tftp=" PCM052_NET_INIT \
		"if tftp ${blimg_addr} "\
		"${tftpdir}${blimg_file}; then " \
		"mtdparts default; " \
		"nand erase.part bootloader; " \
		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
		"${kernel_file}; " \
		"then mtdparts default; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; " \
		"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
	"update_kernel_from_tftp=" PCM052_NET_INIT \
		"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"then setenv fdtsize ${filesize}; " \
		"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
		"mtdparts default; " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${fdtsize}; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
	"update_rootfs_from_tftp=" PCM052_NET_INIT \
		"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"ubi part root; " \
		"ubi create rootfs; " \
		"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
	"update_ramdisk_from_tftp=" PCM052_NET_INIT \
		"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"nand write ${ram_addr} root ${filesize}; fi\0"

/* Miscellaneous configurable options */

#define CONFIG_SYS_MEMTEST_START	0x80010000
#define CONFIG_SYS_MEMTEST_END		0x87C00000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			(0x80000000)
#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE			(8 * 1024)

#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_OFFSET		0xA0000
#define CONFIG_ENV_SIZE_REDUND		(8 * 1024)
#define CONFIG_ENV_OFFSET_REDUND	0xC0000
#endif

#endif
Commit	Line	Data
931a1d2a AA	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Configuration settings for the phytec PCM-052 SoM.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch/imx-regs.h>
	13
931a1d2a AA	14	#define CONFIG_SKIP_LOWLEVEL_INIT
	15
	16	/* Enable passing of ATAGs */
	17	#define CONFIG_CMDLINE_TAG
	18
	19	/* Size of malloc() pool */
	20	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
	21
931a1d2a AA	22	/* Allow to overwrite serial and ethaddr */
931a1d2a AA	23	#define CONFIG_ENV_OVERWRITE
931a1d2a	24
931a1d2a	25	/* NAND support */
931a1d2a AA	26	#define CONFIG_SYS_NAND_ONFI_DETECTION
	27
	28	#ifdef CONFIG_CMD_NAND
931a1d2a AA	29	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	30	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	31
	32	#define CONFIG_JFFS2_NAND
	33
931a1d2a	34	/* Dynamic MTD partition support */
931a1d2a AA	35	#define CONFIG_MTD_PARTITIONS
931a1d2a AA	36	#define CONFIG_MTD_DEVICE
27192d16	37
27192d16 AA	38	#endif
27192d16 AA	39
931a1d2a AA	40	#define CONFIG_FSL_ESDHC
	41	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	42	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	43
	44	/#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1/
931a1d2a	45
931a1d2a AA	46	#define CONFIG_FEC_MXC
	47	#define CONFIG_MII
	48	#define IMX_FEC_BASE ENET_BASE_ADDR
	49	#define CONFIG_FEC_XCV_TYPE RMII
	50	#define CONFIG_FEC_MXC_PHYADDR 0
931a1d2a AA	51
931a1d2a AA	52	/* QSPI Configs*/
931a1d2a AA	53
931a1d2a AA	54	#ifdef CONFIG_FSL_QSPI
931a1d2a AA	55	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	56	#define FSL_QSPI_FLASH_NUM 2
	57	#define CONFIG_SYS_FSL_QSPI_LE
	58	#endif
	59
	60	/* I2C Configs */
931a1d2a AA	61	#define CONFIG_SYS_I2C
	62	#define CONFIG_SYS_I2C_MXC_I2C3
	63	#define CONFIG_SYS_I2C_MXC
	64
	65	/* RTC (actually an RV-4162 but M41T62-compatible) */
931a1d2a AA	66	#define CONFIG_RTC_M41T62
	67	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	68	#define CONFIG_SYS_RTC_BUS_NUM 2
	69
	70	/* EEPROM (24FC256) */
931a1d2a AA	71	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	72	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	73	#define CONFIG_SYS_I2C_EEPROM_BUS 2
	74
931a1d2a AA	75
	76	#define CONFIG_LOADADDR 0x82000000
	77
	78	/* We boot from the gfxRAM area of the OCRAM. */
c0f432c3	79	#define CONFIG_BOARD_SIZE_LIMIT 520192
931a1d2a	80
27192d16 AA	81	/* if no target-specific extra environment settings were defined by the
	82	target, define an empty one */
	83	#ifndef PCM052_EXTRA_ENV_SETTINGS
	84	#define PCM052_EXTRA_ENV_SETTINGS
	85	#endif
	86
	87	/* if no target-specific boot command was defined by the target,
	88	define an empty one */
	89	#ifndef PCM052_BOOTCOMMAND
	90	#define PCM052_BOOTCOMMAND
	91	#endif
	92
	93	/* if no target-specific extra environment settings were defined by the
	94	target, define an empty one */
	95	#ifndef PCM052_NET_INIT
	96	#define PCM052_NET_INIT
	97	#endif
	98
	99	/* boot command, including the target-defined one if any */
	100	#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
	101
	102	/* Extra env settings (including the target-defined ones if any) */
040ef8f5	103	#define CONFIG_EXTRA_ENV_SETTINGS \
27192d16 AA	104	PCM052_EXTRA_ENV_SETTINGS \
27192d16 AA	105	"autoload=no\0" \
040ef8f5 AA	106	"fdt_high=0xffffffff\0" \
040ef8f5 AA	107	"initrd_high=0xffffffff\0" \
ed0c2c0a AA	108	"blimg_file=u-boot.vyb\0" \
ed0c2c0a AA	109	"blimg_addr=0x81000000\0" \
040ef8f5 AA	110	"kernel_file=zImage\0" \
040ef8f5 AA	111	"kernel_addr=0x82000000\0" \
083e4fd4	112	"fdt_file=zImage.dtb\0" \
040ef8f5 AA	113	"fdt_addr=0x81000000\0" \
	114	"ram_file=uRamdisk\0" \
	115	"ram_addr=0x83000000\0" \
	116	"filesys=rootfs.ubifs\0" \
	117	"sys_addr=0x81000000\0" \
	118	"tftploc=/path/to/tftp/directory/\0" \
	119	"nfs_root=/path/to/nfs/root\0" \
	120	"tftptimeout=1000\0" \
	121	"tftptimeoutcountmax=1000000\0" \
43ede0bc	122	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
a7e5f7f3 AA	123	"bootargs_base=setenv bootargs rw " \
a7e5f7f3 AA	124	" mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
040ef8f5 AA	125	"console=ttyLP1,115200n8\0" \
	126	"bootargs_sd=setenv bootargs ${bootargs} " \
	127	"root=/dev/mmcblk0p2 rootwait\0" \
931a1d2a	128	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
040ef8f5 AA	129	"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
040ef8f5 AA	130	"bootargs_nand=setenv bootargs ${bootargs} " \
27f7d4f5	131	"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
040ef8f5 AA	132	"bootargs_ram=setenv bootargs ${bootargs} " \
	133	"root=/dev/ram rw initrd=${ram_addr}\0" \
	134	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	135	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
	136	"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
	137	"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
	138	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	139	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
	140	"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
	141	"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
	142	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	143	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
	144	"nand read ${fdt_addr} dtb; " \
	145	"nand read ${kernel_addr} kernel; " \
	146	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	147	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
	148	"nand read ${fdt_addr} dtb; " \
	149	"nand read ${kernel_addr} kernel; " \
27f7d4f5	150	"nand read ${ram_addr} root; " \
040ef8f5	151	"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
27192d16 AA	152	"update_bootloader_from_tftp=" PCM052_NET_INIT \
27192d16 AA	153	"if tftp ${blimg_addr} "\
ed0c2c0a AA	154	"${tftpdir}${blimg_file}; then " \
ed0c2c0a AA	155	"mtdparts default; " \
040ef8f5	156	"nand erase.part bootloader; " \
ed0c2c0a	157	"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
040ef8f5 AA	158	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
	159	"${kernel_file}; " \
	160	"then mtdparts default; " \
	161	"nand erase.part kernel; " \
	162	"nand write ${kernel_addr} kernel ${filesize}; " \
	163	"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
	164	"nand erase.part dtb; " \
	165	"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
27192d16 AA	166	"update_kernel_from_tftp=" PCM052_NET_INIT \
27192d16 AA	167	"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
040ef8f5 AA	168	"then setenv fdtsize ${filesize}; " \
	169	"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
	170	"mtdparts default; " \
	171	"nand erase.part dtb; " \
	172	"nand write ${fdt_addr} dtb ${fdtsize}; " \
	173	"nand erase.part kernel; " \
	174	"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
27192d16 AA	175	"update_rootfs_from_tftp=" PCM052_NET_INIT \
27192d16 AA	176	"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
040ef8f5 AA	177	"then mtdparts default; " \
	178	"nand erase.part root; " \
	179	"ubi part root; " \
	180	"ubi create rootfs; " \
	181	"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
27192d16 AA	182	"update_ramdisk_from_tftp=" PCM052_NET_INIT \
27192d16 AA	183	"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
040ef8f5	184	"then mtdparts default; " \
27f7d4f5 AA	185	"nand erase.part root; " \
27f7d4f5 AA	186	"nand write ${ram_addr} root ${filesize}; fi\0"
931a1d2a	187
931a1d2a	188	/* Miscellaneous configurable options */
931a1d2a	189
931a1d2a AA	190	#define CONFIG_SYS_MEMTEST_START 0x80010000
	191	#define CONFIG_SYS_MEMTEST_END 0x87C00000
	192
	193	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	194
931a1d2a AA	195	/* Physical memory map */
	196	#define CONFIG_NR_DRAM_BANKS 1
	197	#define PHYS_SDRAM (0x80000000)
a7e5f7f3	198	#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
931a1d2a AA	199
	200	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	201	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	202	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	203
	204	#define CONFIG_SYS_INIT_SP_OFFSET \
	205	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	206	#define CONFIG_SYS_INIT_SP_ADDR \
	207	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	208
e856bdcf	209	/* environment organization */
931a1d2a AA	210	#ifdef CONFIG_ENV_IS_IN_MMC
	211	#define CONFIG_ENV_SIZE (8 * 1024)
	212
	213	#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
	214	#define CONFIG_SYS_MMC_ENV_DEV 0
	215	#endif
	216
	217	#ifdef CONFIG_ENV_IS_IN_NAND
	218	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	219	#define CONFIG_ENV_SIZE (8 * 1024)
040ef8f5	220	#define CONFIG_ENV_OFFSET 0xA0000
931a1d2a	221	#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
040ef8f5	222	#define CONFIG_ENV_OFFSET_REDUND 0xC0000
931a1d2a AA	223	#endif
931a1d2a AA	224
931a1d2a	225	#endif