[people/ms/u-boot.git] / include / configs / pcm052.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the phytec PCM-052 SoM.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

#define CONFIG_SKIP_LOWLEVEL_INIT

/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_NAND_ONFI_DETECTION

#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR

#define CONFIG_JFFS2_NAND

/* Dynamic MTD partition support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE

#ifndef MTDIDS_DEFAULT
#define MTDIDS_DEFAULT			"nand0=NAND"
#endif

#ifndef MTDPARTS_DEFAULT
#define MTDPARTS_DEFAULT		"mtdparts=NAND:640k(bootloader)"\
					",128k(env1)"\
					",128k(env2)"\
					",128k(dtb)"\
					",6144k(kernel)"\
					",-(root)"
#endif

#endif

#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/

#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RMII
#define CONFIG_FEC_MXC_PHYADDR          0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL

/* QSPI Configs*/

#ifdef CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2
#define CONFIG_SYS_FSL_QSPI_LE
#endif

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC

/* RTC (actually an RV-4162 but M41T62-compatible) */
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_RTC_BUS_NUM 2

/* EEPROM (24FC256) */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_BUS 2


#define CONFIG_LOADADDR			0x82000000

/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_TEXT_BASE		0x3f408000
#define CONFIG_BOARD_SIZE_LIMIT		524288

/* if no target-specific extra environment settings were defined by the
   target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS
#define PCM052_EXTRA_ENV_SETTINGS
#endif

/* if no target-specific boot command was defined by the target,
   define an empty one */
#ifndef PCM052_BOOTCOMMAND
#define PCM052_BOOTCOMMAND
#endif

/* if no target-specific extra environment settings were defined by the
   target, define an empty one */
#ifndef PCM052_NET_INIT
#define PCM052_NET_INIT
#endif

/* boot command, including the target-defined one if any */
#define CONFIG_BOOTCOMMAND	PCM052_BOOTCOMMAND "run bootcmd_nand"

/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
	PCM052_EXTRA_ENV_SETTINGS \
	"autoload=no\0" \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"blimg_file=u-boot.vyb\0" \
	"blimg_addr=0x81000000\0" \
	"kernel_file=zImage\0" \
	"kernel_addr=0x82000000\0" \
	"fdt_file=zImage.dtb\0" \
	"fdt_addr=0x81000000\0" \
	"ram_file=uRamdisk\0" \
	"ram_addr=0x83000000\0" \
	"filesys=rootfs.ubifs\0" \
	"sys_addr=0x81000000\0" \
	"tftploc=/path/to/tftp/directory/\0" \
	"nfs_root=/path/to/nfs/root\0" \
	"tftptimeout=1000\0" \
	"tftptimeoutcountmax=1000000\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"bootargs_base=setenv bootargs rw " \
		" mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
		"console=ttyLP1,115200n8\0" \
	"bootargs_sd=setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 rootwait\0" \
	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
		"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
	"bootargs_nand=setenv bootargs ${bootargs} " \
		"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
	"bootargs_ram=setenv bootargs ${bootargs} " \
		"root=/dev/ram rw initrd=${ram_addr}\0" \
	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
		"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
		"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
		"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
		"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"nand read ${ram_addr} root; " \
		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
	"update_bootloader_from_tftp=" PCM052_NET_INIT \
		"if tftp ${blimg_addr} "\
		"${tftpdir}${blimg_file}; then " \
		"mtdparts default; " \
		"nand erase.part bootloader; " \
		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
		"${kernel_file}; " \
		"then mtdparts default; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; " \
		"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
	"update_kernel_from_tftp=" PCM052_NET_INIT \
		"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"then setenv fdtsize ${filesize}; " \
		"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
		"mtdparts default; " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${fdtsize}; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
	"update_rootfs_from_tftp=" PCM052_NET_INIT \
		"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"ubi part root; " \
		"ubi create rootfs; " \
		"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
	"update_ramdisk_from_tftp=" PCM052_NET_INIT \
		"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"nand write ${ram_addr} root ${filesize}; fi\0"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80010000
#define CONFIG_SYS_MEMTEST_END		0x87C00000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			(0x80000000)
#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE			(8 * 1024)

#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_OFFSET		0xA0000
#define CONFIG_ENV_SIZE_REDUND		(8 * 1024)
#define CONFIG_ENV_OFFSET_REDUND	0xC0000
#endif

#endif
Commit	Line	Data
931a1d2a AA	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Configuration settings for the phytec PCM-052 SoM.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch/imx-regs.h>
	13
931a1d2a AA	14	#define CONFIG_SKIP_LOWLEVEL_INIT
	15
	16	/* Enable passing of ATAGs */
	17	#define CONFIG_CMDLINE_TAG
	18
	19	/* Size of malloc() pool */
	20	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
	21
931a1d2a AA	22	/* Allow to overwrite serial and ethaddr */
931a1d2a AA	23	#define CONFIG_ENV_OVERWRITE
931a1d2a	24
931a1d2a AA	25	/* NAND support */
	26	#define CONFIG_CMD_NAND
	27	#define CONFIG_CMD_NAND_TRIMFFS
	28	#define CONFIG_SYS_NAND_ONFI_DETECTION
	29
	30	#ifdef CONFIG_CMD_NAND
931a1d2a AA	31	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	32	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	33
	34	#define CONFIG_JFFS2_NAND
	35
931a1d2a	36	/* Dynamic MTD partition support */
931a1d2a AA	37	#define CONFIG_MTD_PARTITIONS
931a1d2a AA	38	#define CONFIG_MTD_DEVICE
27192d16 AA	39
27192d16 AA	40	#ifndef MTDIDS_DEFAULT
040ef8f5	41	#define MTDIDS_DEFAULT "nand0=NAND"
27192d16 AA	42	#endif
	43
	44	#ifndef MTDPARTS_DEFAULT
27f7d4f5	45	#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
931a1d2a AA	46	",128k(env1)"\
931a1d2a AA	47	",128k(env2)"\
040ef8f5 AA	48	",128k(dtb)"\
040ef8f5 AA	49	",6144k(kernel)"\
27f7d4f5	50	",-(root)"
931a1d2a AA	51	#endif
931a1d2a AA	52
27192d16 AA	53	#endif
27192d16 AA	54
931a1d2a AA	55	#define CONFIG_FSL_ESDHC
	56	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	57	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	58
	59	/#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1/
931a1d2a	60
931a1d2a AA	61	#define CONFIG_FEC_MXC
	62	#define CONFIG_MII
	63	#define IMX_FEC_BASE ENET_BASE_ADDR
	64	#define CONFIG_FEC_XCV_TYPE RMII
	65	#define CONFIG_FEC_MXC_PHYADDR 0
	66	#define CONFIG_PHYLIB
	67	#define CONFIG_PHY_MICREL
	68
	69	/* QSPI Configs*/
931a1d2a AA	70
931a1d2a AA	71	#ifdef CONFIG_FSL_QSPI
931a1d2a AA	72	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	73	#define FSL_QSPI_FLASH_NUM 2
	74	#define CONFIG_SYS_FSL_QSPI_LE
	75	#endif
	76
	77	/* I2C Configs */
931a1d2a AA	78	#define CONFIG_SYS_I2C
	79	#define CONFIG_SYS_I2C_MXC_I2C3
	80	#define CONFIG_SYS_I2C_MXC
	81
	82	/* RTC (actually an RV-4162 but M41T62-compatible) */
931a1d2a AA	83	#define CONFIG_RTC_M41T62
	84	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	85	#define CONFIG_SYS_RTC_BUS_NUM 2
	86
	87	/* EEPROM (24FC256) */
931a1d2a AA	88	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	89	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	90	#define CONFIG_SYS_I2C_EEPROM_BUS 2
	91
931a1d2a AA	92
	93	#define CONFIG_LOADADDR 0x82000000
	94
	95	/* We boot from the gfxRAM area of the OCRAM. */
	96	#define CONFIG_SYS_TEXT_BASE 0x3f408000
	97	#define CONFIG_BOARD_SIZE_LIMIT 524288
	98
27192d16 AA	99	/* if no target-specific extra environment settings were defined by the
	100	target, define an empty one */
	101	#ifndef PCM052_EXTRA_ENV_SETTINGS
	102	#define PCM052_EXTRA_ENV_SETTINGS
	103	#endif
	104
	105	/* if no target-specific boot command was defined by the target,
	106	define an empty one */
	107	#ifndef PCM052_BOOTCOMMAND
	108	#define PCM052_BOOTCOMMAND
	109	#endif
	110
	111	/* if no target-specific extra environment settings were defined by the
	112	target, define an empty one */
	113	#ifndef PCM052_NET_INIT
	114	#define PCM052_NET_INIT
	115	#endif
	116
	117	/* boot command, including the target-defined one if any */
	118	#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
	119
	120	/* Extra env settings (including the target-defined ones if any) */
040ef8f5	121	#define CONFIG_EXTRA_ENV_SETTINGS \
27192d16 AA	122	PCM052_EXTRA_ENV_SETTINGS \
27192d16 AA	123	"autoload=no\0" \
040ef8f5 AA	124	"fdt_high=0xffffffff\0" \
040ef8f5 AA	125	"initrd_high=0xffffffff\0" \
ed0c2c0a AA	126	"blimg_file=u-boot.vyb\0" \
ed0c2c0a AA	127	"blimg_addr=0x81000000\0" \
040ef8f5 AA	128	"kernel_file=zImage\0" \
040ef8f5 AA	129	"kernel_addr=0x82000000\0" \
083e4fd4	130	"fdt_file=zImage.dtb\0" \
040ef8f5 AA	131	"fdt_addr=0x81000000\0" \
	132	"ram_file=uRamdisk\0" \
	133	"ram_addr=0x83000000\0" \
	134	"filesys=rootfs.ubifs\0" \
	135	"sys_addr=0x81000000\0" \
	136	"tftploc=/path/to/tftp/directory/\0" \
	137	"nfs_root=/path/to/nfs/root\0" \
	138	"tftptimeout=1000\0" \
	139	"tftptimeoutcountmax=1000000\0" \
	140	"mtdparts=" MTDPARTS_DEFAULT "\0" \
a7e5f7f3 AA	141	"bootargs_base=setenv bootargs rw " \
a7e5f7f3 AA	142	" mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
040ef8f5 AA	143	"console=ttyLP1,115200n8\0" \
	144	"bootargs_sd=setenv bootargs ${bootargs} " \
	145	"root=/dev/mmcblk0p2 rootwait\0" \
931a1d2a	146	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
040ef8f5 AA	147	"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
040ef8f5 AA	148	"bootargs_nand=setenv bootargs ${bootargs} " \
27f7d4f5	149	"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
040ef8f5 AA	150	"bootargs_ram=setenv bootargs ${bootargs} " \
	151	"root=/dev/ram rw initrd=${ram_addr}\0" \
	152	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	153	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
	154	"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
	155	"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
	156	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	157	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
	158	"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
	159	"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
	160	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	161	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
	162	"nand read ${fdt_addr} dtb; " \
	163	"nand read ${kernel_addr} kernel; " \
	164	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	165	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
	166	"nand read ${fdt_addr} dtb; " \
	167	"nand read ${kernel_addr} kernel; " \
27f7d4f5	168	"nand read ${ram_addr} root; " \
040ef8f5	169	"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
27192d16 AA	170	"update_bootloader_from_tftp=" PCM052_NET_INIT \
27192d16 AA	171	"if tftp ${blimg_addr} "\
ed0c2c0a AA	172	"${tftpdir}${blimg_file}; then " \
ed0c2c0a AA	173	"mtdparts default; " \
040ef8f5	174	"nand erase.part bootloader; " \
ed0c2c0a	175	"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
040ef8f5 AA	176	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
	177	"${kernel_file}; " \
	178	"then mtdparts default; " \
	179	"nand erase.part kernel; " \
	180	"nand write ${kernel_addr} kernel ${filesize}; " \
	181	"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
	182	"nand erase.part dtb; " \
	183	"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
27192d16 AA	184	"update_kernel_from_tftp=" PCM052_NET_INIT \
27192d16 AA	185	"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
040ef8f5 AA	186	"then setenv fdtsize ${filesize}; " \
	187	"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
	188	"mtdparts default; " \
	189	"nand erase.part dtb; " \
	190	"nand write ${fdt_addr} dtb ${fdtsize}; " \
	191	"nand erase.part kernel; " \
	192	"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
27192d16 AA	193	"update_rootfs_from_tftp=" PCM052_NET_INIT \
27192d16 AA	194	"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
040ef8f5 AA	195	"then mtdparts default; " \
	196	"nand erase.part root; " \
	197	"ubi part root; " \
	198	"ubi create rootfs; " \
	199	"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
27192d16 AA	200	"update_ramdisk_from_tftp=" PCM052_NET_INIT \
27192d16 AA	201	"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
040ef8f5	202	"then mtdparts default; " \
27f7d4f5 AA	203	"nand erase.part root; " \
27f7d4f5 AA	204	"nand write ${ram_addr} root ${filesize}; fi\0"
931a1d2a	205
931a1d2a AA	206	/* Miscellaneous configurable options */
931a1d2a AA	207	#define CONFIG_SYS_LONGHELP /* undef to save memory */
931a1d2a AA	208	#define CONFIG_AUTO_COMPLETE
	209	#define CONFIG_CMDLINE_EDITING
	210	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	211	#define CONFIG_SYS_PBSIZE \
	212	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	213	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	214	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	215
931a1d2a AA	216	#define CONFIG_SYS_MEMTEST_START 0x80010000
	217	#define CONFIG_SYS_MEMTEST_END 0x87C00000
	218
	219	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	220
931a1d2a AA	221	/* Physical memory map */
	222	#define CONFIG_NR_DRAM_BANKS 1
	223	#define PHYS_SDRAM (0x80000000)
a7e5f7f3	224	#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
931a1d2a AA	225
	226	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	227	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	228	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	229
	230	#define CONFIG_SYS_INIT_SP_OFFSET \
	231	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	232	#define CONFIG_SYS_INIT_SP_ADDR \
	233	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	234
e856bdcf	235	/* environment organization */
931a1d2a AA	236	#ifdef CONFIG_ENV_IS_IN_MMC
	237	#define CONFIG_ENV_SIZE (8 * 1024)
	238
	239	#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
	240	#define CONFIG_SYS_MMC_ENV_DEV 0
	241	#endif
	242
	243	#ifdef CONFIG_ENV_IS_IN_NAND
	244	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	245	#define CONFIG_ENV_SIZE (8 * 1024)
040ef8f5	246	#define CONFIG_ENV_OFFSET 0xA0000
931a1d2a	247	#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
040ef8f5	248	#define CONFIG_ENV_OFFSET_REDUND 0xC0000
931a1d2a AA	249	#endif
931a1d2a AA	250
931a1d2a	251	#endif