projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a4c8d138 SR |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| a4c8d138 SR |
6 | */ |
| 7 | ||
| 8 | /************************************************************************ | |
| 9 | * pcs440ep.h - configuration for PCS440EP board | |
| 10 | ***********************************************************************/ | |
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 388b82fd BS |
14 | |
| 15 | /* new uImage format support */ | |
| 16 | #define CONFIG_FIT 1 | |
| 17 | #define CONFIG_OF_LIBFDT 1 | |
| 18 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 19 | ||
| a4c8d138 SR |
20 | /*----------------------------------------------------------------------- |
| 21 | * High Level Configuration Options | |
| 22 | *----------------------------------------------------------------------*/ | |
| 23 | #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ | |
| 24 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ | |
| efa35cf1 | 25 | #define CONFIG_440 1 /* ... PPC440 family */ |
| a4c8d138 | 26 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| 2ae18241 WD |
27 | |
| 28 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
| 29 | ||
| a4c8d138 SR |
30 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
| 31 | ||
| 32 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
| 33 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
| 34 | ||
| 35 | /*----------------------------------------------------------------------- | |
| 36 | * Base addresses -- Note these are effective addresses where the | |
| 37 | * actual resources get mapped (not physical addresses) | |
| 38 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
39 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
| 40 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
| 41 | #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN) | |
| 42 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
| 43 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ | |
| 44 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
| 45 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
| 46 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
| 47 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
| a4c8d138 SR |
48 | |
| 49 | /*Don't change either of these*/ | |
| 6d0f6bcf | 50 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
| a4c8d138 SR |
51 | /*Don't change either of these*/ |
| 52 | ||
| 6d0f6bcf JCPV |
53 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
| 54 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
| a4c8d138 SR |
55 | |
| 56 | /*----------------------------------------------------------------------- | |
| 57 | * Initial RAM & stack pointer (placed in SDRAM) | |
| 58 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
59 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
| 60 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
| 553f0982 | 61 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
| 25ddd1fb | 62 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 63 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| a4c8d138 SR |
64 | |
| 65 | /*----------------------------------------------------------------------- | |
| 66 | * Serial Port | |
| 67 | *----------------------------------------------------------------------*/ | |
| 550650dd SR |
68 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 69 | #define CONFIG_SYS_NS16550 | |
| 70 | #define CONFIG_SYS_NS16550_SERIAL | |
| 71 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 72 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
| 6d0f6bcf | 73 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */ |
| a4c8d138 | 74 | #define CONFIG_BAUDRATE 115200 |
| a4c8d138 | 75 | |
| 6d0f6bcf | 76 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| a4c8d138 SR |
77 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 78 | ||
| 79 | /*----------------------------------------------------------------------- | |
| 80 | * Environment | |
| 81 | *----------------------------------------------------------------------*/ | |
| 5a1aceb0 | 82 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
| a4c8d138 SR |
83 | |
| 84 | /*----------------------------------------------------------------------- | |
| 85 | * FLASH related | |
| 86 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
87 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 88 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
| a4c8d138 | 89 | |
| 6d0f6bcf JCPV |
90 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 91 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| a4c8d138 | 92 | |
| 6d0f6bcf JCPV |
93 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
| 94 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
| 95 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
| a4c8d138 | 96 | |
| 6d0f6bcf | 97 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| a4c8d138 | 98 | |
| 5a1aceb0 | 99 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 | 100 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
| 6d0f6bcf | 101 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 | 102 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 566a494f HS |
103 | |
| 104 | #define CONFIG_ENV_OVERWRITE 1 | |
| a4c8d138 SR |
105 | |
| 106 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
107 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 108 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 5a1aceb0 | 109 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
| a4c8d138 | 110 | |
| 566a494f HS |
111 | #define ENV_NAME_REVLEV "revision_level" |
| 112 | #define ENV_NAME_SOLDER "solder_switch" | |
| 113 | #define ENV_NAME_DIP "dip" | |
| 114 | ||
| a4c8d138 SR |
115 | /*----------------------------------------------------------------------- |
| 116 | * DDR SDRAM | |
| 117 | *----------------------------------------------------------------------*/ | |
| 118 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
| 119 | #undef CONFIG_DDR_ECC /* don't use ECC */ | |
| ed4633c9 | 120 | #define SPD_EEPROM_ADDRESS {0x50} |
| 566a494f | 121 | #define CONFIG_PROG_SDRAM_TLB 1 |
| a4c8d138 SR |
122 | |
| 123 | /*----------------------------------------------------------------------- | |
| 124 | * I2C | |
| 125 | *----------------------------------------------------------------------*/ | |
| 126 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
| 127 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| d0b0dcaa | 128 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
| 6d0f6bcf JCPV |
129 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
| 130 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| a4c8d138 | 131 | |
| 6d0f6bcf JCPV |
132 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1) |
| 133 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 134 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 135 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| a4c8d138 SR |
136 | |
| 137 | #define CONFIG_PREBOOT "echo;" \ | |
| 32bf3d14 | 138 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| a4c8d138 SR |
139 | "echo" |
| 140 | ||
| 141 | #undef CONFIG_BOOTARGS | |
| 142 | ||
| 143 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 144 | "netdev=eth0\0" \ | |
| 145 | "hostname=pcs440ep\0" \ | |
| 566a494f HS |
146 | "use_eeprom_ethaddr=default\0" \ |
| 147 | "cs_test=off\0" \ | |
| a4c8d138 SR |
148 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 149 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 150 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 151 | "addip=setenv bootargs ${bootargs} " \ | |
| 152 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 153 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 154 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 155 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 156 | "bootm ${kernel_addr}\0" \ | |
| 157 | "flash_self=run ramargs addip addtty;" \ | |
| 158 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 159 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 160 | "bootm\0" \ | |
| 161 | "rootpath=/opt/eldk/ppc_4xx\0" \ | |
| 162 | "bootfile=/tftpboot/pcs440ep/uImage\0" \ | |
| e461a241 WD |
163 | "kernel_addr=FFF00000\0" \ |
| 164 | "ramdisk_addr=FFF00000\0" \ | |
| a4c8d138 | 165 | "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ |
| e461a241 WD |
166 | "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ |
| 167 | "cp.b 100000 FFFA0000 60000\0" \ | |
| d8ab58b2 | 168 | "upd=run load update\0" \ |
| a4c8d138 SR |
169 | "" |
| 170 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 171 | ||
| 172 | #if 0 | |
| 173 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 174 | #else | |
| 175 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 176 | #endif | |
| 177 | ||
| 566a494f HS |
178 | /* check U-Boot image with SHA1 sum */ |
| 179 | #define CONFIG_SHA1_CHECK_UB_IMG 1 | |
| 6d0f6bcf JCPV |
180 | #define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE |
| 181 | #define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN | |
| 566a494f HS |
182 | |
| 183 | /*----------------------------------------------------------------------- | |
| 184 | * Definitions for status LED | |
| 185 | */ | |
| 186 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
| 187 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
| 188 | ||
| 96e1d75b | 189 | #define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ |
| 6d0f6bcf | 190 | #define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
| 566a494f | 191 | #define STATUS_LED_STATE STATUS_LED_OFF |
| 96e1d75b | 192 | #define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ |
| 6d0f6bcf | 193 | #define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
| 566a494f | 194 | #define STATUS_LED_STATE1 STATUS_LED_ON |
| 96e1d75b | 195 | #define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ |
| 6d0f6bcf | 196 | #define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
| 566a494f | 197 | #define STATUS_LED_STATE2 STATUS_LED_OFF |
| 96e1d75b | 198 | #define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ |
| 6d0f6bcf | 199 | #define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
| 566a494f HS |
200 | #define STATUS_LED_STATE3 STATUS_LED_OFF |
| 201 | ||
| 202 | #define CONFIG_SHOW_BOOT_PROGRESS 1 | |
| 203 | ||
| a4c8d138 SR |
204 | #define CONFIG_BAUDRATE 115200 |
| 205 | ||
| 206 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 207 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| a4c8d138 | 208 | |
| 96e21f86 | 209 | #define CONFIG_PPC4xx_EMAC |
| a4c8d138 | 210 | #define CONFIG_MII 1 /* MII PHY management */ |
| a4c8d138 SR |
211 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 212 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
| 213 | #define CONFIG_PHY1_ADDR 2 | |
| 214 | ||
| 6d0f6bcf | 215 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
| a4c8d138 SR |
216 | |
| 217 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
| 218 | ||
| 219 | /* Partitions */ | |
| 220 | #define CONFIG_MAC_PARTITION | |
| 221 | #define CONFIG_DOS_PARTITION | |
| 222 | #define CONFIG_ISO_PARTITION | |
| 223 | ||
| 224 | #ifdef CONFIG_440EP | |
| 225 | /* USB */ | |
| 226 | #define CONFIG_USB_OHCI | |
| 227 | #define CONFIG_USB_STORAGE | |
| 228 | ||
| 229 | /*Comment this out to enable USB 1.1 device*/ | |
| 230 | #define USB_2_0_DEVICE | |
| 231 | #endif /*CONFIG_440EP*/ | |
| 232 | ||
| 233 | #ifdef DEBUG | |
| 234 | #define CONFIG_PANIC_HANG | |
| 235 | #else | |
| 236 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
| 237 | #endif | |
| 238 | ||
| a4c8d138 | 239 | |
| 079a136c JL |
240 | /* |
| 241 | * BOOTP options | |
| 242 | */ | |
| 243 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 244 | #define CONFIG_BOOTP_BOOTPATH | |
| 245 | #define CONFIG_BOOTP_GATEWAY | |
| 246 | #define CONFIG_BOOTP_HOSTNAME | |
| a4c8d138 | 247 | |
| a4c8d138 | 248 | |
| 26a34560 JL |
249 | /* |
| 250 | * Command line configuration. | |
| 251 | */ | |
| 252 | #include <config_cmd_default.h> | |
| 253 | #define CONFIG_CMD_ASKENV | |
| 254 | #define CONFIG_CMD_DHCP | |
| 255 | #define CONFIG_CMD_DIAG | |
| 256 | #define CONFIG_CMD_EEPROM | |
| 257 | #define CONFIG_CMD_ELF | |
| f98984cb HS |
258 | #define CONFIG_CMD_EXT2 |
| 259 | #define CONFIG_CMD_FAT | |
| 26a34560 | 260 | #define CONFIG_CMD_I2C |
| f98984cb | 261 | #define CONFIG_CMD_IDE |
| 26a34560 JL |
262 | #define CONFIG_CMD_IRQ |
| 263 | #define CONFIG_CMD_MII | |
| 264 | #define CONFIG_CMD_NET | |
| 265 | #define CONFIG_CMD_NFS | |
| 266 | #define CONFIG_CMD_PCI | |
| 267 | #define CONFIG_CMD_PING | |
| 268 | #define CONFIG_CMD_REGINFO | |
| f98984cb | 269 | #define CONFIG_CMD_REISER |
| 26a34560 | 270 | #define CONFIG_CMD_SDRAM |
| 26a34560 | 271 | #define CONFIG_CMD_USB |
| a4c8d138 | 272 | |
| 26a34560 | 273 | #define CONFIG_SUPPORT_VFAT |
| a4c8d138 SR |
274 | |
| 275 | /* | |
| 276 | * Miscellaneous configurable options | |
| 277 | */ | |
| 6d0f6bcf JCPV |
278 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 279 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 26a34560 | 280 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 281 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| a4c8d138 | 282 | #else |
| 6d0f6bcf | 283 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| a4c8d138 | 284 | #endif |
| 6d0f6bcf JCPV |
285 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 286 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 287 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| a4c8d138 | 288 | |
| 6d0f6bcf JCPV |
289 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 290 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| a4c8d138 | 291 | |
| 6d0f6bcf JCPV |
292 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 293 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| a4c8d138 SR |
294 | #define CONFIG_LYNXKDI 1 /* support kdi files */ |
| 295 | ||
| 6d0f6bcf | 296 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| a4c8d138 SR |
297 | |
| 298 | /*----------------------------------------------------------------------- | |
| 299 | * PCI stuff | |
| 300 | *----------------------------------------------------------------------- | |
| 301 | */ | |
| 302 | /* General PCI */ | |
| 303 | #define CONFIG_PCI /* include pci support */ | |
| 842033e6 | 304 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| a4c8d138 SR |
305 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
| 306 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 307 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
| a4c8d138 SR |
308 | |
| 309 | /* Board-specific PCI */ | |
| 6d0f6bcf JCPV |
310 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 311 | #define CONFIG_SYS_PCI_MASTER_INIT | |
| a4c8d138 | 312 | |
| 6d0f6bcf JCPV |
313 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 314 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
| a4c8d138 SR |
315 | |
| 316 | /* | |
| 317 | * For booting Linux, the board info and command line data | |
| 318 | * have to be in the first 8 MB of memory, since this is | |
| 319 | * the maximum mapped by the Linux kernel during initialization. | |
| 320 | */ | |
| 6d0f6bcf | 321 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| a4c8d138 SR |
322 | |
| 323 | /*----------------------------------------------------------------------- | |
| 324 | * External Bus Controller (EBC) Setup | |
| 325 | *----------------------------------------------------------------------*/ | |
| 326 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ | |
| 327 | #define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */ | |
| 328 | ||
| 6d0f6bcf JCPV |
329 | #define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM |
| 330 | #define CONFIG_SYS_SRAM 0xF1000000 | |
| 331 | #define CONFIG_SYS_FPGA 0xF2000000 | |
| 332 | #define CONFIG_SYS_CF1 0xF0000000 | |
| 333 | #define CONFIG_SYS_CF2 0xF0100000 | |
| a4c8d138 SR |
334 | |
| 335 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
336 | #define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */ |
| 337 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ | |
| a4c8d138 SR |
338 | |
| 339 | /* Memory Bank 1 (SRAM) initialization */ | |
| 6d0f6bcf JCPV |
340 | #define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */ |
| 341 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ | |
| a4c8d138 SR |
342 | |
| 343 | /* Memory Bank 2 (FPGA) initialization */ | |
| 6d0f6bcf JCPV |
344 | #define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */ |
| 345 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ | |
| a4c8d138 SR |
346 | |
| 347 | /* Memory Bank 3 (CompactFlash) initialization */ | |
| 6d0f6bcf JCPV |
348 | #define CONFIG_SYS_EBC_PB3AP 0x080BD400 |
| 349 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ | |
| a4c8d138 SR |
350 | |
| 351 | /* Memory Bank 4 (CompactFlash) initialization */ | |
| 6d0f6bcf JCPV |
352 | #define CONFIG_SYS_EBC_PB4AP 0x080BD400 |
| 353 | #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ | |
| a4c8d138 SR |
354 | |
| 355 | /*----------------------------------------------------------------------- | |
| 356 | * PPC440 GPIO Configuration | |
| 357 | */ | |
| 6d0f6bcf | 358 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| a4c8d138 SR |
359 | { \ |
| 360 | /* GPIO Core 0 */ \ | |
| 85f73737 SR |
361 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ |
| 362 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 363 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 364 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 365 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 366 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 367 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 368 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 369 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 370 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 371 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 372 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 373 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ | |
| 374 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ | |
| 375 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ | |
| 376 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ | |
| 377 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ | |
| 378 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ | |
| 379 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ | |
| 380 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ | |
| 381 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ | |
| 382 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ | |
| 383 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ | |
| 384 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ | |
| 385 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ | |
| 386 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ | |
| 387 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ | |
| 388 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 389 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ | |
| 390 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 391 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 392 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| a4c8d138 SR |
393 | }, \ |
| 394 | { \ | |
| 395 | /* GPIO Core 1 */ \ | |
| 85f73737 SR |
396 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ |
| 397 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ | |
| 398 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
| 399 | {GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 400 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ | |
| 401 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ | |
| 402 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
| 403 | {GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
| 404 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ | |
| 405 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 406 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 407 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 408 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 409 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 410 | {GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 411 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 412 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 413 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 414 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
| 415 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
| 416 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 417 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 418 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 419 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 420 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 421 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 422 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 423 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 424 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 425 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 426 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 427 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| a4c8d138 SR |
428 | } \ |
| 429 | } | |
| 430 | ||
| 26a34560 | 431 | #if defined(CONFIG_CMD_KGDB) |
| a4c8d138 SR |
432 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 433 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 434 | #endif | |
| 435 | ||
| 566a494f HS |
436 | /*----------------------------------------------------------------------- |
| 437 | * IDE/ATA stuff Supports IDE harddisk | |
| 438 | *----------------------------------------------------------------------- | |
| 439 | */ | |
| 440 | ||
| 441 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
| 442 | ||
| 443 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 444 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 445 | ||
| 6d0f6bcf JCPV |
446 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 447 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ | |
| 566a494f HS |
448 | |
| 449 | #define CONFIG_IDE_PREINIT 1 | |
| 450 | #define CONFIG_IDE_RESET 1 | |
| 451 | ||
| 6d0f6bcf | 452 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 566a494f | 453 | |
| 6d0f6bcf | 454 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1 |
| 566a494f HS |
455 | |
| 456 | /* Offset for data I/O */ | |
| 6d0f6bcf | 457 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 |
| 566a494f HS |
458 | |
| 459 | /* Offset for normal register accesses */ | |
| 6d0f6bcf | 460 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
| 566a494f HS |
461 | |
| 462 | /* Offset for alternate registers */ | |
| 6d0f6bcf | 463 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0000) |
| 566a494f | 464 | |
| a4c8d138 | 465 | #endif /* __CONFIG_H */ |