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5e4b3361 SR |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************* | |
25 | * (c) 2005 esd gmbh Hannover | |
26 | * | |
27 | * | |
28 | * from IceCube.h file | |
29 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
30 | * | |
31 | *************************************************************************/ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* | |
37 | * High Level Configuration Options | |
38 | * (easy to change) | |
39 | */ | |
40 | ||
41 | #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ | |
42 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
43 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ | |
44 | #define CONFIG_PF5200 1 /* ... on PF5200 board */ | |
45 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
46 | ||
6d0f6bcf | 47 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
5e4b3361 SR |
48 | |
49 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
50 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
51 | ||
31d82672 | 52 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
5e4b3361 SR |
53 | /* |
54 | * Serial console configuration | |
55 | */ | |
56 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
57 | #if 0 /* test-only */ | |
58 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
59 | #else | |
60 | #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ | |
61 | #endif | |
6d0f6bcf | 62 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
5e4b3361 | 63 | |
5e4b3361 SR |
64 | /* |
65 | * PCI Mapping: | |
66 | * 0x40000000 - 0x4fffffff - PCI Memory | |
67 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
68 | */ | |
69 | #define CONFIG_PCI 1 | |
70 | #define CONFIG_PCI_PNP 1 | |
71 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 72 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
5e4b3361 SR |
73 | |
74 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
75 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
76 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
77 | ||
78 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
79 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
80 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
81 | ||
63ff004c | 82 | #define CONFIG_MII 1 |
5e4b3361 SR |
83 | #if 0 /* test-only !!! */ |
84 | #define CONFIG_NET_MULTI 1 | |
85 | #define CONFIG_EEPRO100 1 | |
6d0f6bcf | 86 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
5e4b3361 SR |
87 | #define CONFIG_NS8382X 1 |
88 | #endif | |
5e4b3361 SR |
89 | |
90 | /* Partitions */ | |
91 | #define CONFIG_MAC_PARTITION | |
92 | #define CONFIG_DOS_PARTITION | |
93 | ||
94 | /* USB */ | |
95 | #if 0 | |
96 | #define CONFIG_USB_OHCI | |
5e4b3361 | 97 | #define CONFIG_USB_STORAGE |
5e4b3361 SR |
98 | #endif |
99 | ||
d794cfef | 100 | |
079a136c JL |
101 | /* |
102 | * BOOTP options | |
103 | */ | |
104 | #define CONFIG_BOOTP_BOOTFILESIZE | |
105 | #define CONFIG_BOOTP_BOOTPATH | |
106 | #define CONFIG_BOOTP_GATEWAY | |
107 | #define CONFIG_BOOTP_HOSTNAME | |
108 | ||
109 | ||
5e4b3361 | 110 | /* |
d794cfef | 111 | * Command line configuration. |
5e4b3361 | 112 | */ |
d794cfef JL |
113 | #include <config_cmd_default.h> |
114 | ||
115 | #define CONFIG_CMD_BSP | |
d794cfef JL |
116 | #define CONFIG_CMD_EEPROM |
117 | #define CONFIG_CMD_ELF | |
118 | #define CONFIG_CMD_FAT | |
119 | #define CONFIG_CMD_I2C | |
120 | #define CONFIG_CMD_IDE | |
121 | ||
079a136c | 122 | #define CONFIG_CMD_PCI |
079a136c | 123 | |
5e4b3361 SR |
124 | |
125 | #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ | |
6d0f6bcf JCPV |
126 | # define CONFIG_SYS_LOWBOOT 1 |
127 | # define CONFIG_SYS_LOWBOOT16 1 | |
5e4b3361 SR |
128 | #endif |
129 | #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ | |
6d0f6bcf JCPV |
130 | # define CONFIG_SYS_LOWBOOT 1 |
131 | # define CONFIG_SYS_LOWBOOT08 1 | |
5e4b3361 SR |
132 | #endif |
133 | ||
134 | /* | |
135 | * Autobooting | |
136 | */ | |
137 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
138 | ||
139 | #define CONFIG_PREBOOT "echo;" \ | |
140 | "echo Welcome to ParaFinder pf5200;" \ | |
141 | "echo" | |
142 | ||
143 | #undef CONFIG_BOOTARGS | |
144 | ||
145 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
146 | "netdev=eth0\0" \ | |
147 | "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ | |
148 | "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ | |
fe126d8b WD |
149 | "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ |
150 | "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ | |
151 | "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ | |
5e4b3361 SR |
152 | "loadaddr=01000000\0" \ |
153 | "serverip=192.168.2.99\0" \ | |
154 | "gatewayip=10.0.0.79\0" \ | |
155 | "user=mu\0" \ | |
156 | "target=pf5200.esd\0" \ | |
157 | "script=pf5200.bat\0" \ | |
158 | "image=/tftpboot/vxWorks_pf5200\0" \ | |
159 | "ipaddr=10.0.13.196\0" \ | |
160 | "netmask=255.255.0.0\0" \ | |
161 | "" | |
162 | ||
163 | #define CONFIG_BOOTCOMMAND "run flash_vxworks0" | |
164 | ||
5e4b3361 SR |
165 | /* |
166 | * IPB Bus clocking configuration. | |
167 | */ | |
6d0f6bcf | 168 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
5e4b3361 SR |
169 | /* |
170 | * I2C configuration | |
171 | */ | |
172 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 173 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
5e4b3361 | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ |
176 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
5e4b3361 SR |
177 | |
178 | /* | |
179 | * EEPROM configuration | |
180 | */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
182 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
183 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
184 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
185 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 | |
5e4b3361 SR |
186 | /* |
187 | * Flash configuration | |
188 | */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
190 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
191 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) | |
192 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
193 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
5e4b3361 | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
196 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
5e4b3361 SR |
197 | |
198 | /* | |
199 | * Environment settings | |
200 | */ | |
201 | #if 1 /* test-only */ | |
5a1aceb0 | 202 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
203 | #define CONFIG_ENV_SIZE 0x10000 |
204 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
5e4b3361 SR |
205 | #define CONFIG_ENV_OVERWRITE 1 |
206 | #else | |
bb1f8b4f | 207 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
208 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ |
209 | #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ | |
5e4b3361 SR |
210 | /* total size of a CAT24WC32 is 8192 bytes */ |
211 | #define CONFIG_ENV_OVERWRITE 1 | |
212 | #endif | |
213 | ||
214 | /* | |
215 | * Memory map | |
216 | */ | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MBAR 0xF0000000 |
218 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
219 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
5e4b3361 SR |
220 | |
221 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
223 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
5e4b3361 | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
226 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
227 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
5e4b3361 | 228 | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
230 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
231 | # define CONFIG_SYS_RAMBOOT 1 | |
5e4b3361 SR |
232 | #endif |
233 | ||
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
235 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
236 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
5e4b3361 SR |
237 | |
238 | /* | |
239 | * Ethernet configuration | |
240 | */ | |
241 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 242 | #define CONFIG_MPC5xxx_FEC_MII100 |
5e4b3361 | 243 | /* |
86321fc1 | 244 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
5e4b3361 | 245 | */ |
86321fc1 | 246 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
5e4b3361 SR |
247 | #define CONFIG_PHY_ADDR 0x00 |
248 | #define CONFIG_UDP_CHECKSUM 1 | |
249 | ||
250 | /* | |
251 | * GPIO configuration | |
252 | */ | |
6d0f6bcf | 253 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 |
5e4b3361 SR |
254 | |
255 | /* | |
256 | * Miscellaneous configurable options | |
257 | */ | |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
259 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d794cfef | 260 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 261 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5e4b3361 | 262 | #else |
6d0f6bcf | 263 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5e4b3361 | 264 | #endif |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
266 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
267 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5e4b3361 | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
270 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
5e4b3361 | 271 | |
6d0f6bcf | 272 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
5e4b3361 | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
5e4b3361 | 275 | |
6d0f6bcf | 276 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
5e4b3361 | 277 | |
6d0f6bcf | 278 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 279 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 280 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
281 | #endif |
282 | ||
5e4b3361 SR |
283 | /* |
284 | * Various low-level settings | |
285 | */ | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
287 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
5e4b3361 | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
290 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
291 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 | |
5e4b3361 | 292 | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
294 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
5e4b3361 | 295 | |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_CS1_START 0xfd000000 |
297 | #define CONFIG_SYS_CS1_SIZE 0x00010000 | |
298 | #define CONFIG_SYS_CS1_CFG 0x10101410 | |
5e4b3361 | 299 | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_CS_BURST 0x00000000 |
301 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
5e4b3361 | 302 | |
6d0f6bcf | 303 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
5e4b3361 SR |
304 | |
305 | /*----------------------------------------------------------------------- | |
306 | * USB stuff | |
307 | *----------------------------------------------------------------------- | |
308 | */ | |
309 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
310 | #define CONFIG_USB_CONFIG 0x00001000 | |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * IDE/ATA stuff Supports IDE harddisk | |
314 | *----------------------------------------------------------------------- | |
315 | */ | |
316 | ||
317 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
318 | ||
319 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
320 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
321 | ||
322 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
323 | #define CONFIG_IDE_PREINIT | |
324 | ||
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
326 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
5e4b3361 | 327 | |
6d0f6bcf | 328 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
5e4b3361 | 329 | |
6d0f6bcf | 330 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
5e4b3361 SR |
331 | |
332 | /* Offset for data I/O */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
5e4b3361 SR |
334 | |
335 | /* Offset for normal register accesses */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
5e4b3361 SR |
337 | |
338 | /* Offset for alternate registers */ | |
6d0f6bcf | 339 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
5e4b3361 SR |
340 | |
341 | /* Interval between registers */ | |
6d0f6bcf | 342 | #define CONFIG_SYS_ATA_STRIDE 4 |
5e4b3361 SR |
343 | |
344 | /*----------------------------------------------------------------------- | |
345 | * CPLD stuff | |
346 | */ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ |
348 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ | |
5e4b3361 SR |
349 | |
350 | /* CPLD program pin configuration */ | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ |
352 | #define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ | |
353 | #define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ | |
354 | #define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ | |
5e4b3361 | 355 | |
6d0f6bcf JCPV |
356 | #define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ |
357 | #define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ | |
358 | #define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ | |
359 | #define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ | |
5e4b3361 | 360 | |
6d0f6bcf | 361 | #define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) |
5e4b3361 SR |
362 | #define JTAG_GPIO_CFG_SET 0x00000000 |
363 | #define JTAG_GPIO_CFG_RESET 0x00F00000 | |
364 | ||
6d0f6bcf | 365 | #define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) |
5e4b3361 SR |
366 | #define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ |
367 | #define JTAG_GPIO_TMS_EN_RESET 0x00000000 | |
6d0f6bcf | 368 | #define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) |
5e4b3361 SR |
369 | #define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ |
370 | #define JTAG_GPIO_TMS_DDR_RESET 0x00000000 | |
371 | ||
6d0f6bcf | 372 | #define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) |
5e4b3361 SR |
373 | #define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ |
374 | #define JTAG_GPIO_TCK_EN_RESET 0x00000000 | |
6d0f6bcf | 375 | #define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) |
5e4b3361 SR |
376 | #define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ |
377 | #define JTAG_GPIO_TCK_DDR_RESET 0x00000000 | |
378 | ||
6d0f6bcf | 379 | #define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) |
5e4b3361 SR |
380 | #define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ |
381 | #define JTAG_GPIO_TDI_EN_RESET 0x00000000 | |
6d0f6bcf | 382 | #define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) |
5e4b3361 SR |
383 | #define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ |
384 | #define JTAG_GPIO_TDI_DDR_RESET 0x00000000 | |
385 | ||
6d0f6bcf | 386 | #define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) |
5e4b3361 SR |
387 | #define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ |
388 | #define JTAG_GPIO_TDO_EN_RESET 0x00000000 | |
6d0f6bcf | 389 | #define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) |
5e4b3361 SR |
390 | #define JTAG_GPIO_TDO_DDR_SET 0x00000000 |
391 | #define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ | |
392 | ||
393 | #endif /* __CONFIG_H */ |