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b5d289fc AD |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Ilko Iliev <iliev@ronetix.at> | |
4 | * Asen Dimov <dimov@ronetix.at> | |
5 | * Ronetix GmbH <www.ronetix.at> | |
6 | * | |
7 | * (C) Copyright 2007-2008 | |
c9e798d3 | 8 | * Stelian Pop <stelian@popies.net> |
b5d289fc AD |
9 | * Lead Tech Design <www.leadtechdesign.com> |
10 | * | |
11 | * Configuation settings for the PM9G45 board. | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
b5d289fc AD |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
eb6e608b AD |
19 | /* |
20 | * SoC must be defined first, before hardware.h is included. | |
21 | * In this case SoC is defined in boards.cfg. | |
22 | */ | |
23 | #include <asm/hardware.h> | |
24 | ||
b5d289fc | 25 | #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ |
eb6e608b | 26 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" |
b5d289fc | 27 | |
a3e09cc2 AD |
28 | #define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 |
29 | ||
b5d289fc AD |
30 | /* ARM asynchronous clock */ |
31 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ | |
eb6e608b | 32 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
eb6e608b | 33 | #define CONFIG_SYS_TEXT_BASE 0x73f00000 |
b5d289fc AD |
34 | |
35 | #define CONFIG_ARCH_CPU_INIT | |
36 | ||
37 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
38 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
39 | #define CONFIG_INITRD_TAG 1 | |
40 | ||
41 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
b5d289fc AD |
42 | |
43 | /* | |
44 | * Hardware drivers | |
45 | */ | |
46 | #define CONFIG_AT91_GPIO 1 | |
47 | #define CONFIG_ATMEL_USART 1 | |
eb6e608b AD |
48 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
49 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
b5d289fc AD |
50 | |
51 | #define CONFIG_SYS_USE_NANDFLASH 1 | |
52 | ||
53 | /* LED */ | |
54 | #define CONFIG_AT91_LED | |
bcf9fe37 AB |
55 | #define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ |
56 | #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ | |
b5d289fc | 57 | |
b5d289fc AD |
58 | |
59 | /* | |
60 | * BOOTP options | |
61 | */ | |
62 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
63 | #define CONFIG_BOOTP_BOOTPATH 1 | |
64 | #define CONFIG_BOOTP_GATEWAY 1 | |
65 | #define CONFIG_BOOTP_HOSTNAME 1 | |
66 | ||
67 | /* | |
68 | * Command line configuration. | |
69 | */ | |
b5d289fc | 70 | #define CONFIG_CMD_NAND 1 |
b5d289fc AD |
71 | |
72 | #define CONFIG_CMD_JFFS2 1 | |
73 | #define CONFIG_JFFS2_CMDLINE 1 | |
74 | #define CONFIG_JFFS2_NAND 1 | |
75 | #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ | |
76 | #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ | |
77 | #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ | |
78 | ||
79 | /* SDRAM */ | |
80 | #define CONFIG_NR_DRAM_BANKS 1 | |
81 | #define PHYS_SDRAM 0x70000000 | |
82 | #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ | |
83 | ||
b5d289fc AD |
84 | /* NAND flash */ |
85 | #ifdef CONFIG_CMD_NAND | |
b5d289fc AD |
86 | #define CONFIG_NAND_ATMEL |
87 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
88 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
89 | #define CONFIG_SYS_NAND_DBW_8 1 | |
90 | /* our ALE is AD21 */ | |
91 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
92 | /* our CLE is AD22 */ | |
93 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
ac45bb16 AB |
94 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
95 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) | |
b5d289fc AD |
96 | |
97 | #endif | |
98 | ||
99 | /* Ethernet */ | |
100 | #define CONFIG_MACB 1 | |
101 | #define CONFIG_RMII 1 | |
b5d289fc AD |
102 | #define CONFIG_NET_RETRY_COUNT 20 |
103 | #define CONFIG_RESET_PHY_R 1 | |
104 | ||
105 | /* USB */ | |
106 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 107 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
b5d289fc | 108 | #define CONFIG_USB_OHCI_NEW 1 |
b5d289fc AD |
109 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
110 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ | |
111 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" | |
112 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
b5d289fc AD |
113 | |
114 | /* board specific(not enough SRAM) */ | |
115 | #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 | |
116 | ||
117 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ | |
118 | ||
119 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
120 | #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE | |
121 | ||
122 | /* bootstrap + u-boot + env + linux in nandflash */ | |
123 | #define CONFIG_ENV_IS_IN_NAND 1 | |
124 | #define CONFIG_ENV_OFFSET 0x60000 | |
125 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
126 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
127 | #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" | |
128 | #define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \ | |
129 | "console=ttyS0,115200 " \ | |
130 | "root=/dev/mtdblock4 " \ | |
131 | "mtdparts=atmel_nand:128k(bootstrap)ro," \ | |
132 | "256k(uboot)ro,1664k(env)," \ | |
133 | "2M(linux)ro,-(root) rw " \ | |
134 | "rootfstype=jffs2" | |
135 | ||
136 | #define CONFIG_BAUDRATE 115200 | |
b5d289fc | 137 | |
b5d289fc AD |
138 | #define CONFIG_SYS_CBSIZE 256 |
139 | #define CONFIG_SYS_MAXARGS 16 | |
140 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
141 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
142 | #define CONFIG_SYS_LONGHELP 1 | |
143 | #define CONFIG_CMDLINE_EDITING 1 | |
144 | #define CONFIG_AUTO_COMPLETE | |
b5d289fc AD |
145 | |
146 | /* | |
147 | * Size of malloc() pool | |
148 | */ | |
149 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ | |
150 | 0x1000) | |
b5d289fc | 151 | |
510f794c AD |
152 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
153 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
154 | GENERATED_GBL_DATA_SIZE) | |
155 | ||
b5d289fc | 156 | #endif |