[people/ms/u-boot.git] / include / configs / porter.h

/*
 * include/configs/porter.h
 *     This file is Porter board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __PORTER_H
#define __PORTER_H

#undef DEBUG
#define CONFIG_R8A7791
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0x70000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE6304000
#endif

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(1024u * 1024 * 1024)

/* SCIF */
#define CONFIG_SCIF_CONSOLE

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)

#define CONFIG_SYS_TMU_CLK_DIV	4

/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH		4
#define CONFIG_SH_I2C_DATA_LOW		5
#define CONFIG_SH_I2C_CLOCK		10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR	0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* SD */
#define CONFIG_SH_SDHI_FREQ	97500000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA	0x00200000

#endif /* __PORTER_H */
Commit	Line	Data
60c0467a VB	1	/*
	2	* include/configs/porter.h
	3	* This file is Porter board configuration.
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Copyright (C) 2015 Cogent Embedded, Inc.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0
	9	*/
	10
	11	#ifndef __PORTER_H
	12	#define __PORTER_H
	13
	14	#undef DEBUG
	15	#define CONFIG_R8A7791
1cc95f6e	16	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
60c0467a VB	17
	18	#include "rcar-gen2-common.h"
	19
1cc95f6e	20	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
60c0467a VB	21	#define CONFIG_SYS_TEXT_BASE 0x70000000
	22	#else
	23	#define CONFIG_SYS_TEXT_BASE 0xE6304000
	24	#endif
	25
1cc95f6e	26	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
60c0467a VB	27	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
	28	#else
	29	#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
	30	#endif
	31	#define STACK_AREA_SIZE 0xC000
	32	#define LOW_LEVEL_MERAM_STACK \
	33	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	34
	35	/* MEMORY */
	36	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	37	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	38	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
	39
	40	/* SCIF */
	41	#define CONFIG_SCIF_CONSOLE
	42
	43	/* FLASH */
	44	#define CONFIG_SPI
60c0467a	45	#define CONFIG_SH_QSPI
60c0467a	46	#define CONFIG_SPI_FLASH_QUAD
60c0467a VB	47
60c0467a VB	48	/* SH Ether */
60c0467a VB	49	#define CONFIG_SH_ETHER
	50	#define CONFIG_SH_ETHER_USE_PORT 0
	51	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	52	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	53	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	54	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	55	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	56	#define CONFIG_PHYLIB
	57	#define CONFIG_PHY_MICREL
	58	#define CONFIG_BITBANGMII
	59	#define CONFIG_BITBANGMII_MULTI
	60
	61	/* Board Clock */
	62	#define RMOBILE_XTAL_CLK 20000000u
	63	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	64	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
	65	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	66	#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
	67
	68	#define CONFIG_SYS_TMU_CLK_DIV 4
	69
	70	/* i2c */
60c0467a VB	71	#define CONFIG_SYS_I2C
	72	#define CONFIG_SYS_I2C_SH
	73	#define CONFIG_SYS_I2C_SLAVE 0x7F
	74	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
	75	#define CONFIG_SYS_I2C_SH_SPEED0 400000
	76	#define CONFIG_SYS_I2C_SH_SPEED1 400000
	77	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	78	#define CONFIG_SH_I2C_DATA_HIGH 4
	79	#define CONFIG_SH_I2C_DATA_LOW 5
	80	#define CONFIG_SH_I2C_CLOCK 10000000
	81
	82	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	83
	84	/* USB */
	85	#define CONFIG_USB_EHCI
	86	#define CONFIG_USB_EHCI_RMOBILE
	87	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
60c0467a VB	88
60c0467a VB	89	/* SD */
60c0467a VB	90	#define CONFIG_SH_SDHI_FREQ 97500000
	91
	92	/* Module stop status bits */
	93	/* INTC-RT */
	94	#define CONFIG_SMSTP0_ENA 0x00400000
	95	/* MSIF */
	96	#define CONFIG_SMSTP2_ENA 0x00002000
	97	/* INTC-SYS, IRQC */
	98	#define CONFIG_SMSTP4_ENA 0x00000180
	99	/* SCIF0 */
	100	#define CONFIG_SMSTP7_ENA 0x00200000
	101
	102	#endif /* __PORTER_H */