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60fbe254 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * This file contains the configuration parameters for the PURPLE board. | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | #define CONFIG_MIPS32 1 /* MIPS 5Kc CPU core */ | |
32 | #define CONFIG_PURPLE 1 /* on a PURPLE Board */ | |
33 | ||
34 | #define CPU_CLOCK_RATE 125000000 /* 125 MHz clock for the MIPS core */ | |
35 | #define ASC_CLOCK_RATE 62500000 /* 62.5 MHz ASC clock */ | |
36 | ||
37 | #define INFINEON_EBU_BOOTCFG 0xE0CC | |
38 | ||
39 | #define CONFIG_STACKSIZE (128 * 1024) | |
40 | ||
41 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
42 | ||
43 | #define CONFIG_BAUDRATE 19200 | |
44 | ||
45 | /* valid baudrates */ | |
6d0f6bcf | 46 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
60fbe254 WD |
47 | |
48 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
49 | ||
50 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 51 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
60fbe254 WD |
52 | "echo" |
53 | ||
54 | #undef CONFIG_BOOTARGS | |
55 | ||
56 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
57 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 58 | "nfsroot=${serverip}:${rootpath}\0" \ |
60fbe254 | 59 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
60 | "addip=setenv bootargs ${bootargs} " \ |
61 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
62 | ":${hostname}:${netdev}:off\0" \ | |
63 | "addmisc=setenv bootargs ${bootargs} " \ | |
64 | "console=ttyS0,${baudrate} " \ | |
65 | "ethaddr=${ethaddr} " \ | |
60fbe254 WD |
66 | "panic=1\0" \ |
67 | "flash_nfs=run nfsargs addip addmisc;" \ | |
fe126d8b | 68 | "bootm ${kernel_addr}\0" \ |
60fbe254 | 69 | "flash_self=run ramargs addip addmisc;" \ |
fe126d8b WD |
70 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
71 | "net_nfs=tftp 80500000 ${bootfile};" \ | |
60fbe254 WD |
72 | "run nfsargs addip addmisc;bootm\0" \ |
73 | "rootpath=/opt/eldk/mips_5KC\0" \ | |
74 | "bootfile=/tftpboot/purple/uImage\0" \ | |
75 | "kernel_addr=B0040000\0" \ | |
76 | "ramdisk_addr=B0100000\0" \ | |
77 | "u-boot=/tftpboot/purple/u-boot.bin\0" \ | |
fe126d8b | 78 | "load=tftp 80500000 ${u-boot}\0" \ |
60fbe254 | 79 | "update=protect off 1:0-4;era 1:0-4;" \ |
fe126d8b | 80 | "cp.b 80500000 B0000000 ${filesize}\0" \ |
60fbe254 WD |
81 | "" |
82 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
83 | ||
26a34560 | 84 | |
079a136c JL |
85 | /* |
86 | * BOOTP options | |
87 | */ | |
88 | #define CONFIG_BOOTP_BOOTFILESIZE | |
89 | #define CONFIG_BOOTP_BOOTPATH | |
90 | #define CONFIG_BOOTP_GATEWAY | |
91 | #define CONFIG_BOOTP_HOSTNAME | |
92 | ||
93 | ||
26a34560 JL |
94 | /* |
95 | * Command line configuration. | |
96 | */ | |
97 | #include <config_cmd_default.h> | |
98 | ||
99 | #define CONFIG_CMD_ELF | |
100 | ||
60fbe254 | 101 | |
6d0f6bcf | 102 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
60fbe254 | 103 | |
6d0f6bcf | 104 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
60fbe254 | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
60fbe254 | 107 | |
6d0f6bcf | 108 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
60fbe254 WD |
109 | |
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
114 | #define CONFIG_SYS_PROMPT "PURPLE # " /* Monitor Command Prompt */ | |
115 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
116 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
117 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2) | |
118 | #define CONFIG_SYS_HZ 1000 | |
119 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
60fbe254 | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ |
60fbe254 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MEMTEST_START 0x80200000 |
124 | #define CONFIG_SYS_MEMTEST_END 0x80800000 | |
60fbe254 WD |
125 | |
126 | #define CONFIG_MISC_INIT_R | |
127 | ||
128 | /*----------------------------------------------------------------------- | |
129 | * FLASH and environment organization | |
130 | */ | |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
132 | #define CONFIG_SYS_MAX_FLASH_SECT (35) /* max number of sectors on one chip */ | |
60fbe254 WD |
133 | |
134 | #define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ | |
135 | ||
136 | /* The following #defines are needed to get flash environment right */ | |
14d0a02a | 137 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 138 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) |
60fbe254 | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
60fbe254 WD |
141 | |
142 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_FLASH_ERASE_TOUT (6 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
144 | #define CONFIG_SYS_FLASH_WRITE_TOUT (6 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
60fbe254 | 145 | |
5a1aceb0 | 146 | #define CONFIG_ENV_IS_IN_FLASH 1 |
60fbe254 WD |
147 | |
148 | /* Address and size of Primary Environment Sector */ | |
0e8d1586 JCPV |
149 | #define CONFIG_ENV_ADDR 0xB0008000 |
150 | #define CONFIG_ENV_SIZE 0x4000 | |
60fbe254 WD |
151 | |
152 | #define CONFIG_FLASH_32BIT | |
153 | #define CONFIG_NR_DRAM_BANKS 1 | |
154 | ||
155 | #define CONFIG_PLB2800_ETHER | |
156 | #define CONFIG_NET_MULTI | |
157 | ||
158 | /*----------------------------------------------------------------------- | |
159 | * Cache Configuration | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
162 | #define CONFIG_SYS_ICACHE_SIZE 16384 | |
163 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
60fbe254 WD |
164 | |
165 | /* | |
166 | * Temporary buffer for serial data until the real serial driver | |
167 | * is initialised (memtest will destroy this buffer) | |
168 | */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_SCONSOLE_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - \ |
170 | CONFIG_SYS_DCACHE_SIZE / 2) | |
171 | #define CONFIG_SYS_SCONSOLE_SIZE (CONFIG_SYS_DCACHE_SIZE / 4) | |
60fbe254 WD |
172 | |
173 | #endif /* __CONFIG_H */ |