[people/ms/u-boot.git] / include / configs / qemu-ppce500.h

/*
 * Copyright 2011-2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Corenet DS style board configuration file
 */
#ifndef __QEMU_PPCE500_H
#define __QEMU_PPCE500_H

#define CONFIG_CMD_REGINFO

/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_QEMU_E500

#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */

#define CONFIG_SYS_MPC85XX_NO_RESETVEC

#define CONFIG_SYS_RAMBOOT

#define CONFIG_PCI			/* Enable PCI/PCIE */
#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

/* Needed to fill the ccsrbar pointer */
#define CONFIG_BOARD_EARLY_INIT_F

/* Virtual address to CCSRBAR */
#define CONFIG_SYS_CCSRBAR		0xe0000000
/* Physical address should be a function call */
#ifndef __ASSEMBLY__
extern unsigned long long get_phys_ccsrbar_addr_early(void);
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#endif

#define CONFIG_PHYS_64BIT

/* Virtual address range for PCI region maps */
#define CONFIG_SYS_PCI_MAP_START	0x80000000
#define CONFIG_SYS_PCI_MAP_END		0xe8000000

/* Virtual address to a temporary map if we need it (max 128MB) */
#define CONFIG_SYS_TMPVIRT		0xe8000000

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_CHIP_SELECTS_PER_CTRL	0

#define CONFIG_SYS_CLK_FREQ        33000000

#define CONFIG_SYS_NO_FLASH

#define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#define CONFIG_ENV_IS_NOWHERE

#define CONFIG_HWCONFIG

#define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif	/* CONFIG_PCI */

#define CONFIG_LBA48
#define CONFIG_DOS_PARTITION

/*
 * Environment
 */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO		/* echo on for serial download */

#define CONFIG_LAST_STAGE_INIT

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IRQ

#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_BAUDRATE	115200

#define CONFIG_BOOTCOMMAND		\
	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"

#endif	/* __QEMU_PPCE500_H */
Commit	Line	Data
fa08d395 AG	1	/*
	2	* Copyright 2011-2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	/*
	8	* Corenet DS style board configuration file
	9	*/
	10	#ifndef __QEMU_PPCE500_H
	11	#define __QEMU_PPCE500_H
	12
	13	#define CONFIG_CMD_REGINFO
	14
	15	/* High Level Configuration Options */
	16	#define CONFIG_BOOKE
	17	#define CONFIG_E500 /* BOOKE e500 family */
	18	#define CONFIG_QEMU_E500
	19
	20	#undef CONFIG_SYS_TEXT_BASE
	21	#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
	22
	23	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	24
	25	#define CONFIG_SYS_RAMBOOT
	26
	27	#define CONFIG_PCI /* Enable PCI/PCIE */
	28	#define CONFIG_PCI1 1 /* PCI controller 1 */
	29	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	30	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	31
	32	#define CONFIG_ENV_OVERWRITE
	33
	34	#define CONFIG_ENABLE_36BIT_PHYS
	35
	36	#define CONFIG_ADDR_MAP
	37	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	38
	39	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	40	#define CONFIG_SYS_MEMTEST_END 0x00400000
	41	#define CONFIG_SYS_ALT_MEMTEST
	42	#define CONFIG_PANIC_HANG /* do not reset board on panic */
	43
	44	/* Needed to fill the ccsrbar pointer */
	45	#define CONFIG_BOARD_EARLY_INIT_F
	46
	47	/* Virtual address to CCSRBAR */
	48	#define CONFIG_SYS_CCSRBAR 0xe0000000
	49	/* Physical address should be a function call */
	50	#ifndef __ASSEMBLY__
	51	extern unsigned long long get_phys_ccsrbar_addr_early(void);
e834975b AG	52	#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
	53	#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
	54	#else
	55	#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
	56	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
fa08d395	57	#endif
e834975b AG	58
e834975b AG	59	#define CONFIG_PHYS_64BIT
fa08d395 AG	60
	61	/* Virtual address range for PCI region maps */
	62	#define CONFIG_SYS_PCI_MAP_START 0x80000000
	63	#define CONFIG_SYS_PCI_MAP_END 0xe8000000
	64
	65	/* Virtual address to a temporary map if we need it (max 128MB) */
	66	#define CONFIG_SYS_TMPVIRT 0xe8000000
	67
	68	/*
	69	* DDR Setup
	70	*/
	71	#define CONFIG_VERY_BIG_RAM
	72	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	73	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	74
	75	#define CONFIG_CHIP_SELECTS_PER_CTRL 0
	76
	77	#define CONFIG_SYS_CLK_FREQ 33000000
	78
	79	#define CONFIG_SYS_NO_FLASH
	80
	81	#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
	82
	83	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	84
	85	#define CONFIG_ENV_IS_NOWHERE
	86
	87	#define CONFIG_HWCONFIG
	88
	89	#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
	90	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
	91	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
	92	/* The assembler doesn't like typecast */
	93	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	94	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	95	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	96	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	97
	98	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	99	GENERATED_GBL_DATA_SIZE)
	100	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	101
	102	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	103	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	104
	105	#define CONFIG_CONS_INDEX 1
fa08d395 AG	106	#define CONFIG_SYS_NS16550_SERIAL
	107	#define CONFIG_SYS_NS16550_REG_SIZE 1
	108	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
	109
	110	#define CONFIG_SYS_BAUDRATE_TABLE \
	111	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	112
	113	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	114	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	115
fa08d395 AG	116	/*
	117	* General PCI
	118	* Memory space is mapped 1-1, but I/O space must start from 0.
	119	*/
	120
	121	#ifdef CONFIG_PCI
	122	#define CONFIG_PCI_INDIRECT_BRIDGE
fa08d395	123	#define CONFIG_PCI_PNP /* do pci plug-and-play */
fa08d395 AG	124
	125	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	126	#define CONFIG_DOS_PARTITION
	127	#endif /* CONFIG_PCI */
	128
	129	#define CONFIG_LBA48
	130	#define CONFIG_DOS_PARTITION
fa08d395 AG	131
	132	/*
	133	* Environment
	134	*/
	135	#define CONFIG_ENV_SIZE 0x2000
	136
	137	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	138
	139	#define CONFIG_LAST_STAGE_INIT
	140
	141	/*
	142	* Command line configuration.
	143	*/
fa08d395	144	#define CONFIG_CMD_IRQ
fa08d395 AG	145
	146	#ifdef CONFIG_PCI
	147	#define CONFIG_CMD_PCI
fa08d395 AG	148	#endif
	149
	150	/*
	151	* Miscellaneous configurable options
	152	*/
	153	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	154	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	155	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	156	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	157	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	158	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	159	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	160	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
	161
	162	/*
	163	* For booting Linux, the board info and command line data
	164	* have to be in the first 64 MB of memory, since this is
	165	* the maximum mapped by the Linux kernel during initialization.
	166	*/
	167	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	168	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	169
	170	/*
	171	* Environment Configuration
	172	*/
	173	#define CONFIG_ROOTPATH "/opt/nfsroot"
	174	#define CONFIG_BOOTFILE "uImage"
	175	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
	176
	177	/* default location for tftp and bootm */
	178	#define CONFIG_LOADADDR 1000000
	179
	180	#define CONFIG_BAUDRATE 115200
	181
fa08d395 AG	182	#define CONFIG_BOOTCOMMAND \
	183	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
	184
	185	#endif /* __QEMU_PPCE500_H */