[people/ms/u-boot.git] / include / configs / qong.h

/*
 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
 *
 * Configuration settings for the Dave/DENX QongEVB-LITE board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_MX31			/* This is a mx31 */
#define CONFIG_QONG

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TEXT_BASE 0xa0000000

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1536 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

#define CONFIG_MXC_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG

#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13XXX

#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	100000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32

/* FPGA */
#define CONFIG_FPGA
#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE	(CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT	1

#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_DNET
#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)

/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)

/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	2
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */

/*
 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
 * initial TFTP transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

#endif /* CONFIG_QONG_FPGA */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_UNZIP

#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	5

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"uboot_addr=A0000000\0"						\
	"kernel_addr=A00C0000\0"					\
	"ramdisk_addr=A0300000\0"					\
	"u-boot=qong/u-boot.bin\0"					\
	"kernel_addr_r=80800000\0"					\
	"hostname=qong\0"						\
	"bootfile=qong/uImage\0"					\
	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm\0"						\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\
	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\
		"vmode:0\0"						\

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
		sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* memtest works on first 255MB of RAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */

#define CONFIG_MISC_INIT_R

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */

/*
 * NAND driver
 */

#ifndef __ASSEMBLY__
extern void qong_nand_plat_init(void *chip);
extern int qong_nand_rdy(void *chip);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE	CS3_BASE
#define NAND_PLAT_INIT() qong_nand_plat_init(nand)

#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
#define QONG_NAND_WRITE(addr, cmd) \
	do { \
		__REG8(addr) = cmd; \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip)      (qong_nand_rdy(chip))

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	1024
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */

#define	CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* Flash memory is CFI compliant */
#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Filesystem
 */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,"		\
				"nand0=gen_nand"
#define MTDPARTS_DEFAULT	\
	"mtdparts=physmap-flash.0:"				\
			"512k(U-Boot),128k(env1),128k(env2),"	\
			"2304k(kernel),13m(ramdisk),-(user);"	\
		"gen_nand:"					\
			"128m(nand)"

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

#define CONFIG_BOARD_EARLY_INIT_F

#endif /* __CONFIG_H */
Commit	Line	Data
0d19f6c8 IY	1	/*
	2	* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
	3	*
	4	* Configuration settings for the Dave/DENX QongEVB-LITE board.
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
0d19f6c8 IY	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
86271115	12	#include <asm/arch/imx-regs.h>
0d19f6c8	13
22a9ea97	14	/* High Level Configuration Options */
3fd968e9	15	#define CONFIG_MX31 /* This is a mx31 */
8a508e30	16	#define CONFIG_QONG
0d19f6c8 IY	17
	18	#define CONFIG_DISPLAY_CPUINFO
	19	#define CONFIG_DISPLAY_BOARDINFO
	20
22a9ea97 SB	21	#define CONFIG_SYS_TEXT_BASE 0xa0000000
22a9ea97 SB	22
8a508e30 FE	23	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	24	#define CONFIG_SETUP_MEMORY_TAGS
	25	#define CONFIG_INITRD_TAG
0d19f6c8 IY	26
	27	/*
	28	* Size of malloc() pool
	29	*/
544aa66a	30	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
0d19f6c8 IY	31
	32	/*
	33	* Hardware drivers
	34	*/
	35
40f6fffe SB	36	#define CONFIG_MXC_UART
40f6fffe SB	37	#define CONFIG_MXC_UART_BASE UART1_BASE
0d19f6c8	38
c4ea1424	39	#define CONFIG_MXC_GPIO
8640c984	40	#define CONFIG_HW_WATCHDOG
abbab703	41	#define CONFIG_IMX_WATCHDOG
45997e0a	42
e98ecd71 SB	43	#define CONFIG_MXC_SPI
e98ecd71 SB	44	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	45	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
4e8b7544	46	#define CONFIG_RTC_MC13XXX
e98ecd71	47
be3b51aa ŁM	48	#define CONFIG_POWER
	49	#define CONFIG_POWER_SPI
	50	#define CONFIG_POWER_FSL
e98ecd71 SB	51	#define CONFIG_FSL_PMIC_BUS 1
	52	#define CONFIG_FSL_PMIC_CS 0
	53	#define CONFIG_FSL_PMIC_CLK 100000
9f481e95	54	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
f33bd087	55	#define CONFIG_FSL_PMIC_BITLEN 32
e98ecd71	56
0d19f6c8	57	/* FPGA */
b9eb3fdf	58	#define CONFIG_FPGA
8a508e30	59	#define CONFIG_QONG_FPGA
0d19f6c8	60	#define CONFIG_FPGA_BASE (CS1_BASE)
b9eb3fdf SB	61	#define CONFIG_FPGA_LATTICE
b9eb3fdf SB	62	#define CONFIG_FPGA_COUNT 1
0d19f6c8 IY	63
	64	#ifdef CONFIG_QONG_FPGA
	65	/* Ethernet */
8a508e30	66	#define CONFIG_DNET
0d19f6c8	67	#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
0d19f6c8	68
7c8cf0d0	69	/* Framebuffer and LCD */
62a22dca HR	70	#define CONFIG_VIDEO
62a22dca HR	71	#define CONFIG_CFB_CONSOLE
7c8cf0d0	72	#define CONFIG_VIDEO_MX3
62a22dca HR	73	#define CONFIG_VIDEO_LOGO
	74	#define CONFIG_VIDEO_SW_CURSOR
	75	#define CONFIG_VGA_AS_SINGLE_DEVICE
7c8cf0d0	76	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
62a22dca	77	#define CONFIG_SPLASH_SCREEN
7c8cf0d0 SB	78	#define CONFIG_CMD_BMP
7c8cf0d0 SB	79	#define CONFIG_BMP_16BPP
544aa66a WD	80	#define CONFIG_VIDEO_BMP_GZIP
544aa66a WD	81	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
7c8cf0d0	82
d7dc464b SB	83	/* USB */
	84	#define CONFIG_CMD_USB
	85	#ifdef CONFIG_CMD_USB
	86	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	87	#define CONFIG_USB_EHCI_MXC
	88	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	89	#define CONFIG_MXC_USB_PORT 2
	90	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT)
	91	#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
	92	#define CONFIG_EHCI_IS_TDI
	93	#define CONFIG_USB_STORAGE
	94	#define CONFIG_DOS_PARTITION
	95	#define CONFIG_SUPPORT_VFAT
b952c24a	96	#define CONFIG_CMD_EXT2
d7dc464b SB	97	#define CONFIG_CMD_FAT
	98	#endif /* CONFIG_CMD_USB */
	99
0d19f6c8 IY	100	/*
	101	* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
	102	* initial TFTP transfer, should the user wish one, significantly.
	103	*/
	104	#define CONFIG_ARP_TIMEOUT 200UL
	105
	106	#endif /* CONFIG_QONG_FPGA */
	107
	108	#define CONFIG_CONS_INDEX 1
	109	#define CONFIG_BAUDRATE 115200
0d19f6c8 IY	110
	111	/***********************************************************
	112	* Command definition
	113	***********************************************************/
7e4a9e6d	114	#define CONFIG_CMD_CACHE
b952c24a	115	#define CONFIG_CMD_DATE
0d19f6c8	116	#define CONFIG_CMD_DHCP
0d19f6c8	117	#define CONFIG_CMD_MII
45997e0a	118	#define CONFIG_CMD_NAND
b952c24a	119	#define CONFIG_CMD_PING
e98ecd71	120	#define CONFIG_CMD_SPI
544aa66a	121	#define CONFIG_CMD_UNZIP
0d19f6c8	122
9660e442	123	#define CONFIG_BOARD_LATE_INIT
0d19f6c8 IY	124
	125	#define CONFIG_BOOTDELAY 5
	126
	127	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	128
0d19f6c8 IY	129	#define CONFIG_EXTRA_ENV_SETTINGS \
	130	"netdev=eth0\0" \
	131	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	132	"nfsroot=${serverip}:${rootpath}\0" \
	133	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	134	"addip=setenv bootargs ${bootargs} " \
	135	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	136	":${hostname}:${netdev}:off panic=1\0" \
	137	"addtty=setenv bootargs ${bootargs}" \
	138	" console=ttymxc0,${baudrate}\0" \
b4e85d0f	139	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
0d19f6c8	140	"addmisc=setenv bootargs ${bootargs}\0" \
8a1cdaa9	141	"uboot_addr=A0000000\0" \
b952c24a	142	"kernel_addr=A00C0000\0" \
8a1cdaa9	143	"ramdisk_addr=A0300000\0" \
b4e85d0f	144	"u-boot=qong/u-boot.bin\0" \
0d19f6c8 IY	145	"kernel_addr_r=80800000\0" \
	146	"hostname=qong\0" \
	147	"bootfile=qong/uImage\0" \
	148	"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
b4e85d0f	149	"flash_self=run ramargs addip addtty addmtd addmisc;" \
0d19f6c8	150	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
b4e85d0f	151	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8 IY	152	"bootm ${kernel_addr}\0" \
0d19f6c8 IY	153	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
b4e85d0f	154	"run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8	155	"bootm\0" \
b4e85d0f IY	156	"bootcmd=run flash_self\0" \
b4e85d0f IY	157	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0 MV	158	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
93ea89f0 MV	159	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
0d19f6c8	160	" +${filesize};cp.b ${fileaddr} " \
93ea89f0	161	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
0d19f6c8	162	"upd=run load update\0" \
62a22dca HR	163	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
	164	"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
	165	"vmode:0\0" \
0d19f6c8 IY	166
	167	/*
	168	* Miscellaneous configurable options
	169	*/
	170	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b4e85d0f	171	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
0d19f6c8 IY	172	/* Print Buffer Size */
	173	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	174	sizeof(CONFIG_SYS_PROMPT) + 16)
	175	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	176	/* Boot Argument Buffer Size */
	177	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	178
	179	/* memtest works on first 255MB of RAM */
	180	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	181	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
	182
	183	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	184
8a508e30 FE	185	#define CONFIG_CMDLINE_EDITING
8a508e30 FE	186	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
0d19f6c8	187
8a508e30	188	#define CONFIG_MISC_INIT_R
0d19f6c8 IY	189
	190	/*-----------------------------------------------------------------------
	191	* Physical Memory Map
	192	*/
	193	#define CONFIG_NR_DRAM_BANKS 1
	194	#define PHYS_SDRAM_1 CSD0_BASE
	195	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	196
45997e0a SB	197	/*
	198	* NAND driver
	199	*/
	200
	201	#ifndef __ASSEMBLY__
	202	extern void qong_nand_plat_init(void *chip);
	203	extern int qong_nand_rdy(void *chip);
	204	#endif
	205	#define CONFIG_NAND_PLAT
	206	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	207	#define CONFIG_SYS_NAND_BASE CS3_BASE
	208	#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
	209
	210	#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 24))
	211	#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 23))
	212	#define QONG_NAND_WRITE(addr, cmd) \
	213	do { \
	214	__REG8(addr) = cmd; \
	215	} while (0)
	216
	217	#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
	218	#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
	219	#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
	220
0d19f6c8 IY	221	/*-----------------------------------------------------------------------
	222	* FLASH and environment organization
	223	*/
	224	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	225	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	226	/* max number of sectors on one chip */
	227	#define CONFIG_SYS_MAX_FLASH_SECT 1024
	228	/* Monitor at beginning of flash */
	229	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	230	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
	231
8a508e30	232	#define CONFIG_ENV_IS_IN_FLASH
0d19f6c8 IY	233	#define CONFIG_ENV_SECT_SIZE 0x20000
0d19f6c8 IY	234	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
d7dc464b	235	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
0d19f6c8 IY	236
	237	/* Address and size of Redundant Environment Sector */
	238	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	239	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	240
	241	/*-----------------------------------------------------------------------
	242	* CFI FLASH driver setup
	243	*/
	244	/* Flash memory is CFI compliant */
8a508e30	245	#define CONFIG_SYS_FLASH_CFI
0d19f6c8	246	/* Use drivers/cfi_flash.c */
8a508e30	247	#define CONFIG_FLASH_CFI_DRIVER
0d19f6c8	248	/* Use buffered writes (~10x faster) */
8a508e30	249	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
0d19f6c8	250	/* Use hardware sector protection */
8a508e30	251	#define CONFIG_SYS_FLASH_PROTECTION
0d19f6c8 IY	252
0d19f6c8 IY	253	/*
c9d944d3	254	* Filesystem
0d19f6c8	255	*/
c9d944d3 SB	256	#define CONFIG_CMD_JFFS2
	257	#define CONFIG_CMD_UBI
	258	#define CONFIG_CMD_UBIFS
	259	#define CONFIG_RBTREE
	260	#define CONFIG_MTD_PARTITIONS
68d7d651	261	#define CONFIG_CMD_MTDPARTS
c9d944d3	262	#define CONFIG_LZO
942556a9 SR	263	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	264	#define CONFIG_FLASH_CFI_MTD
b952c24a WD	265	#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
b952c24a WD	266	"nand0=gen_nand"
b4e85d0f	267	#define MTDPARTS_DEFAULT \
b952c24a WD	268	"mtdparts=physmap-flash.0:" \
	269	"512k(U-Boot),128k(env1),128k(env2)," \
	270	"2304k(kernel),13m(ramdisk),-(user);" \
	271	"gen_nand:" \
	272	"128m(nand)"
0d19f6c8	273
a784c01a	274	/* additions for new relocation code, must be added to all boards */
e48b7c0a HS	275	#define CONFIG_SYS_SDRAM_BASE 0x80000000
e48b7c0a HS	276	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982	277	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
25ddd1fb	278	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
e48b7c0a HS	279	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
e48b7c0a HS	280
8a508e30	281	#define CONFIG_BOARD_EARLY_INIT_F
e48b7c0a	282
0d19f6c8	283	#endif /* __CONFIG_H */