[people/ms/u-boot.git] / include / configs / quantum.h

/*
 * (C) Copyright 2003-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 * changes for 16M board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#undef CONFIG_MPC860
#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_RPXLITE		1	/* QUANTUM is the RPXlite clone */
#define CONFIG_RMU		1   /* The QUNATUM is based on our RMU */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

/* default developmenmt environment */

#define CONFIG_ETHADDR 00:0B:17:00:00:00

#define CONFIG_IPADDR  10.10.69.10
#define CONFIG_SERVERIP 10.10.69.49
#define CONFIG_NETMASK	255.255.255.0
#define CONFIG_HOSTNAME QUANTUM
#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"

#define CONFIG_BOOTARGS	 "root=/dev/ram rw"

#define CONFIG_BOOTCOMMAND "bootm ff000000"

#define CONFIG_EXTRA_ENV_SETTINGS \
    "serial#=12345\0"		\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
	"ramargs=setenv bootargs root=/dev/ram rw\0" \
    "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"

/*
 * Select the more full-featured memory test (Barr embedded systems)
 */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
#define CONFIG_RTC_M48T35A 1

#if 0
#define CONFIG_WATCHDOG 1		/* watchdog enabled		*/
#else
#undef CONFIG_WATCHDOG
#endif

/*  NVRAM and RTC */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
#define CONFIG_SYS_NVRAM_SIZE 2048


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_AUTOBOOT_KEYED	/* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT		\
	"\nEnter password - autoboot in %d sec...\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"system"
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00040000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFA200000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE	0xFF000000

#if 1
    #define CONFIG_FLASH_CFI_DRIVER
#else
    #undef CONFIG_FLASH_CFI_DRIVER
#endif


#ifdef CONFIG_FLASH_CFI_DRIVER
    #define CONFIG_SYS_FLASH_CFI 1
    #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
    #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#endif

/*%%% #define CONFIG_SYS_FLASH_BASE		0xFFF00000 */
#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	0xFFF00000
/*%%% #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	    0x00040000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/* FPGA */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_FPGA_SPARTAN2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK


/*-----------------------------------------------------------------------
 * Reset address
 */
#define CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER 0x2002000F*/
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */

/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)

#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00

#define CONFIG_SYS_OR1_PRELIM	(0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/* RPXLITE mem setting */
#define CONFIG_SYS_BR3_PRELIM	0xFA400001		/* FPGA */
#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910

#define CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	20

/*
 * Refresh clock Prescalar
 */
#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)

/*
 * BCSRx
 *
 * Board Status and Control Registers
 *
 */

#define BCSR0 0xFA400000
#define BCSR1 0xFA400001
#define BCSR2 0xFA400002
#define BCSR3 0xFA400003

#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
#define BCSR0_COLTEST	0x20
#define BCSR0_ETHLPBK	0x40
#define BCSR0_ETHEN	0x80

#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
#define BCSR1_PCVCTL6	0x02
#define BCSR1_PCVCTL5	0x04
#define BCSR1_PCVCTL4	0x08
#define BCSR1_IPB5SEL	0x10

#define BCSR2_ENPA5HDR	0x08	/* USB Control */
#define BCSR2_ENUSBCLK	0x10
#define BCSR2_USBPWREN	0x20
#define BCSR2_USBSPD	0x40
#define BCSR2_USBSUSP	0x80

#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
#define BCSR3_D27	0x10	/* Dip Switch settings */
#define BCSR3_D26	0x20
#define BCSR3_D25	0x40
#define BCSR3_D24	0x80

#endif	/* __CONFIG_H */
Commit	Line	Data
da93ed81	1	/*
cd0402a7	2	* (C) Copyright 2003-2010
da93ed81 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
da93ed81 WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
da93ed81 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	* changes for 16M board
	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
	20
	21	#undef CONFIG_MPC860
	22	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	23	#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
	24	#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	27
da93ed81 WD	28	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	29	#undef CONFIG_8xx_CONS_SMC2
	30	#undef CONFIG_8xx_CONS_NONE
	31	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
	32	#if 0
	33	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	34	#else
	35	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	36	#endif
	37
	38	/* default developmenmt environment */
	39
da93ed81 WD	40	#define CONFIG_ETHADDR 00:0B:17:00:00:00
	41
	42	#define CONFIG_IPADDR 10.10.69.10
	43	#define CONFIG_SERVERIP 10.10.69.49
	44	#define CONFIG_NETMASK 255.255.255.0
	45	#define CONFIG_HOSTNAME QUANTUM
8b3637c6	46	#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
da93ed81 WD	47
	48	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	49
	50	#define CONFIG_BOOTCOMMAND "bootm ff000000"
	51
	52	#define CONFIG_EXTRA_ENV_SETTINGS \
	53	"serial#=12345\0" \
fe126d8b	54	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
da93ed81	55	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b	56	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
da93ed81 WD	57
	58	/*
	59	* Select the more full-featured memory test (Barr embedded systems)
	60	*/
6d0f6bcf	61	#define CONFIG_SYS_ALT_MEMTEST
da93ed81 WD	62
da93ed81 WD	63	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	64	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
da93ed81 WD	65
	66
	67	/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
	68	#define CONFIG_RTC_M48T35A 1
	69
	70	#if 0
	71	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
	72	#else
	73	#undef CONFIG_WATCHDOG
	74	#endif
	75
	76	/* NVRAM and RTC */
6d0f6bcf JCPV	77	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
6d0f6bcf JCPV	78	#define CONFIG_SYS_NVRAM_SIZE 2048
da93ed81 WD	79
da93ed81 WD	80
90cc3eb6 JL	81	/*
	82	* Command line configuration.
	83	*/
	84	#include <config_cmd_default.h>
da93ed81	85
90cc3eb6 JL	86	#define CONFIG_CMD_DATE
	87	#define CONFIG_CMD_DHCP
	88	#define CONFIG_CMD_NFS
	89	#define CONFIG_CMD_PING
	90	#define CONFIG_CMD_REGINFO
	91	#define CONFIG_CMD_SNTP
da93ed81	92
90cc3eb6	93
d3b8c1a7 JL	94	/*
	95	* BOOTP options
	96	*/
	97	#define CONFIG_BOOTP_SUBNETMASK
	98	#define CONFIG_BOOTP_GATEWAY
	99	#define CONFIG_BOOTP_HOSTNAME
	100	#define CONFIG_BOOTP_BOOTPATH
	101	#define CONFIG_BOOTP_BOOTFILESIZE
	102
da93ed81 WD	103
da93ed81 WD	104	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
c37207d7 WD	105	#define CONFIG_AUTOBOOT_PROMPT \
c37207d7 WD	106	"\nEnter password - autoboot in %d sec...\n", bootdelay
da93ed81 WD	107	#define CONFIG_AUTOBOOT_DELAY_STR "system"
	108	/*
	109	* Miscellaneous configurable options
	110	*/
6d0f6bcf	111	#define CONFIG_SYS_LONGHELP /* undef to save memory */
90cc3eb6	112	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	113	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
da93ed81	114	#else
6d0f6bcf	115	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
da93ed81	116	#endif
6d0f6bcf JCPV	117	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	118	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	119	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
da93ed81	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */
6d0f6bcf JCPV	122	#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
da93ed81	123
6d0f6bcf	124	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
da93ed81	125
da93ed81 WD	126	/*
	127	* Low Level Configuration Settings
	128	* (address mappings, register initial values, etc.)
	129	* You should know what you are doing if you make changes here.
	130	*/
	131	/*-----------------------------------------------------------------------
	132	* Internal Memory Mapped Register
	133	*/
6d0f6bcf	134	#define CONFIG_SYS_IMMR 0xFA200000
da93ed81 WD	135
	136	/*-----------------------------------------------------------------------
	137	* Definitions for initial stack pointer and data area (in DPRAM)
	138	*/
6d0f6bcf	139	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	140	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	141	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	142	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
da93ed81 WD	143
	144	/*-----------------------------------------------------------------------
	145	* Start addresses for the final memory configuration
	146	* (Set up by the startup code)
6d0f6bcf	147	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
da93ed81	148	*/
6d0f6bcf JCPV	149	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	150	#define CONFIG_SYS_FLASH_BASE 0xFF000000
da93ed81 WD	151
da93ed81 WD	152	#if 1
00b1883a	153	#define CONFIG_FLASH_CFI_DRIVER
da93ed81	154	#else
00b1883a	155	#undef CONFIG_FLASH_CFI_DRIVER
da93ed81 WD	156	#endif
	157
	158
00b1883a	159	#ifdef CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	160	#define CONFIG_SYS_FLASH_CFI 1
	161	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	162	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
da93ed81 WD	163	#endif
da93ed81 WD	164
6d0f6bcf	165	/%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 /
90cc3eb6	166	#if defined(DEBUG) \|\| defined(CONFIG_CMD_IDE)
6d0f6bcf	167	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
da93ed81	168	#else
6d0f6bcf	169	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
da93ed81	170	#endif
6d0f6bcf JCPV	171	#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
	172	/%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /
	173	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
da93ed81 WD	174
	175	/*
	176	* For booting Linux, the board info and command line data
	177	* have to be in the first 8 MB of memory, since this is
	178	* the maximum mapped by the Linux kernel during initialization.
	179	*/
6d0f6bcf	180	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
da93ed81 WD	181
	182	/*-----------------------------------------------------------------------
	183	* FLASH organization
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
da93ed81	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
da93ed81	190
5a1aceb0	191	#define CONFIG_ENV_IS_IN_FLASH 1
cd0402a7	192	#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
0e8d1586 JCPV	193	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
0e8d1586 JCPV	194	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf	195	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
da93ed81 WD	196
da93ed81 WD	197	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	198	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	199	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
da93ed81 WD	200
	201	/* FPGA */
	202	#define CONFIG_MISC_INIT_R
6d0f6bcf JCPV	203	#define CONFIG_SYS_FPGA_SPARTAN2
6d0f6bcf JCPV	204	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
da93ed81 WD	205
	206
	207	/*-----------------------------------------------------------------------
	208	* Reset address
	209	*/
6d0f6bcf	210	#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
da93ed81 WD	211
	212	/*-----------------------------------------------------------------------
	213	* Cache Configuration
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
90cc3eb6	216	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	217	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
da93ed81 WD	218	#endif
	219
	220	/*-----------------------------------------------------------------------
	221	* SYPCR - System Protection Control 11-9
	222	* SYPCR can only be written once after reset!
	223	*-----------------------------------------------------------------------
	224	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	225	*/
	226	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	227	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
da93ed81 WD	228	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
da93ed81 WD	229	#else
6d0f6bcf	230	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| 0x00000600 \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
da93ed81 WD	231	#endif
	232
	233	/*-----------------------------------------------------------------------
	234	* SIUMCR - SIU Module Configuration 11-6
	235	*-----------------------------------------------------------------------
	236	* PCMCIA config., multi-function pin tri-state
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
da93ed81 WD	239
	240	/*-----------------------------------------------------------------------
	241	* TBSCR - Time Base Status and Control 11-26
	242	*-----------------------------------------------------------------------
	243	* Clear Reference Interrupt Status, Timebase freezing enabled
	244	*/
6d0f6bcf	245	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF \| TBSCR_TBE)
da93ed81 WD	246
	247	/*-----------------------------------------------------------------------
	248	* RTCSC - Real-Time Clock Status and Control Register 11-27
	249	*-----------------------------------------------------------------------
	250	*/
6d0f6bcf JCPV	251	/%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE) /
6d0f6bcf JCPV	252	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_RTE)
da93ed81 WD	253
	254	/*-----------------------------------------------------------------------
	255	* PISCR - Periodic Interrupt Status and Control 11-31
	256	*-----------------------------------------------------------------------
	257	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	258	*/
6d0f6bcf	259	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
da93ed81 WD	260
	261	/*-----------------------------------------------------------------------
	262	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	263	*-----------------------------------------------------------------------
	264	* Reset PLL lock status sticky bit, timer expired status bit and timer
	265	* interrupt status bit
	266	*
	267	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	268	*/
	269	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	270	#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) \| PLPRCR_TEXPS )
da93ed81 WD	271
	272	/*-----------------------------------------------------------------------
	273	* SCCR - System Clock and reset Control Register 15-27
	274	*-----------------------------------------------------------------------
	275	* Set clock output, timebase and RTC source and divider,
	276	* power management and some other internal clocks
	277	*/
	278	#define SCCR_MASK SCCR_EBDF00
	279	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	280	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_TBS)
da93ed81 WD	281
	282	/*-----------------------------------------------------------------------
	283	* PCMCIA stuff
	284	*-----------------------------------------------------------------------
	285	*
	286	*/
6d0f6bcf JCPV	287	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	288	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	289	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	290	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	291	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	292	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	293	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	294	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
da93ed81 WD	295
	296	/*-----------------------------------------------------------------------
	297	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	298	*-----------------------------------------------------------------------
	299	*/
	300
8d1165e1	301	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
da93ed81 WD	302	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	303
	304	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	305	#undef CONFIG_IDE_LED /* LED for ide not supported */
	306	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	307
6d0f6bcf JCPV	308	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	309	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
da93ed81	310
6d0f6bcf	311	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
da93ed81	312
6d0f6bcf	313	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
da93ed81 WD	314
da93ed81 WD	315	/* Offset for data I/O */
6d0f6bcf	316	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
da93ed81 WD	317
da93ed81 WD	318	/* Offset for normal register accesses */
6d0f6bcf	319	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
da93ed81 WD	320
da93ed81 WD	321	/* Offset for alternate registers */
6d0f6bcf	322	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
da93ed81 WD	323
	324	/*-----------------------------------------------------------------------
	325	*
	326	*-----------------------------------------------------------------------
	327	*
	328	*/
6d0f6bcf JCPV	329	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	330	#define CONFIG_SYS_DER 0
da93ed81 WD	331
	332	/*
	333	* Init Memory Controller:
	334	*
	335	* BR0 and OR0 (FLASH)
	336	*/
	337
	338	#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
6d0f6bcf	339	#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
da93ed81 WD	340
da93ed81 WD	341	/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
6d0f6bcf	342	#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK \| OR_BI)
da93ed81	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	345	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) \| BR_V)
da93ed81 WD	346
	347	/*
	348	* BR1 and OR1 (SDRAM)
	349	*
	350	*/
	351	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
	352	#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
	353
	354	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	355	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
da93ed81	356
6d0f6bcf JCPV	357	#define CONFIG_SYS_OR1_PRELIM (0xF0000000 \| CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
6d0f6bcf JCPV	358	#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
da93ed81 WD	359
da93ed81 WD	360	/* RPXLITE mem setting */
6d0f6bcf JCPV	361	#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */
6d0f6bcf JCPV	362	#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
da93ed81	363
6d0f6bcf JCPV	364	#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
6d0f6bcf JCPV	365	#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
da93ed81 WD	366
	367	/*
	368	* Memory Periodic Timer Prescaler
	369	*/
	370
	371	/* periodic timer for refresh */
6d0f6bcf	372	#define CONFIG_SYS_MAMR_PTA 20
da93ed81 WD	373
	374	/*
	375	* Refresh clock Prescalar
	376	*/
6d0f6bcf	377	#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
da93ed81 WD	378
	379	/*
	380	* MAMR settings for SDRAM
	381	*/
	382
	383	/* 9 column SDRAM */
6d0f6bcf	384	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
da93ed81 WD	385	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	386	MAMR_RLFA_16X \| MAMR_WLFA_16X \| MAMR_TLFA_16X)
	387
da93ed81 WD	388	/*
	389	* BCSRx
	390	*
	391	* Board Status and Control Registers
	392	*
	393	*/
	394
	395	#define BCSR0 0xFA400000
	396	#define BCSR1 0xFA400001
	397	#define BCSR2 0xFA400002
	398	#define BCSR3 0xFA400003
	399
	400	#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
	401	#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
	402	#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
	403	#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
	404	#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
	405	#define BCSR0_COLTEST 0x20
	406	#define BCSR0_ETHLPBK 0x40
	407	#define BCSR0_ETHEN 0x80
	408
	409	#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
	410	#define BCSR1_PCVCTL6 0x02
	411	#define BCSR1_PCVCTL5 0x04
	412	#define BCSR1_PCVCTL4 0x08
	413	#define BCSR1_IPB5SEL 0x10
	414
	415	#define BCSR2_ENPA5HDR 0x08 /* USB Control */
	416	#define BCSR2_ENUSBCLK 0x10
	417	#define BCSR2_USBPWREN 0x20
	418	#define BCSR2_USBSPD 0x40
	419	#define BCSR2_USBSUSP 0x80
	420
	421	#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
	422	#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
	423	#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
	424	#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
	425	#define BCSR3_D27 0x10 /* Dip Switch settings */
	426	#define BCSR3_D26 0x20
	427	#define BCSR3_D25 0x40
	428	#define BCSR3_D24 0x80
	429
	430	#endif /* __CONFIG_H */