[people/ms/u-boot.git] / include / configs / r0p7734.h

/*
 * Configuation settings for the Renesas Solutions r0p7734 board
 *
 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __R0P7734_H
#define __R0P7734_H

#define CONFIG_CPU_SH7734	1
#define CONFIG_R0P7734		1
#define CONFIG_400MHZ_MODE	1
/* #define CONFIG_533MHZ_MODE	1 */

#define CONFIG_SYS_TEXT_BASE 0x8FFC0000

#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC3,115200"

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#ifndef CONFIG_SH_ETHER
# define CONFIG_SMC911X
# define CONFIG_SMC911X_16_BIT
# define CONFIG_SMC911X_BASE (0x84000000)
#endif

/* I2C */
#define CONFIG_SH_SH7734_I2C	1
#define CONFIG_HARD_I2C			1
#define CONFIG_I2C_MULTI_BUS	1
#define CONFIG_SYS_MAX_I2C_BUS	2
#define CONFIG_SYS_I2C_MODULE	0
#define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE	0x50
#define CONFIG_SH_I2C_DATA_HIGH	4
#define CONFIG_SH_I2C_DATA_LOW	5
#define CONFIG_SH_I2C_CLOCK		500000000
#define CONFIG_SH_I2C_BASE0		0xFFC70000
#define CONFIG_SH_I2C_BASE1		0xFFC7100

/* undef to save memory	*/
#define CONFIG_SYS_LONGHELP
/* Monitor Command Prompt */
/* Buffer size for input from the Console */
#define CONFIG_SYS_CBSIZE		256
/* Buffer size for Console output */
#define CONFIG_SYS_PBSIZE		256
/* max args accepted for monitor commands */
#define CONFIG_SYS_MAXARGS		16
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE	512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_SCIF			1
#define CONFIG_CONS_SCIF3	1

/* Suppress display of console information at boot */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#if defined(CONFIG_400MHZ_MODE)
#define CONFIG_SYS_CLK_FREQ 50000000
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV      4

#endif	/* __R0P7734_H */
Commit	Line	Data
8ca805e1 NI	1	/*
	2	* Configuation settings for the Renesas Solutions r0p7734 board
	3	*
	4	* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8ca805e1 NI	7	*/
	8
	9	#ifndef __R0P7734_H
	10	#define __R0P7734_H
	11
8ca805e1 NI	12	#define CONFIG_CPU_SH7734 1
	13	#define CONFIG_R0P7734 1
	14	#define CONFIG_400MHZ_MODE 1
	15	/* #define CONFIG_533MHZ_MODE 1 */
	16
	17	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
	18
8ca805e1 NI	19	#define CONFIG_CMD_SDRAM
8ca805e1 NI	20	#define CONFIG_CMD_ENV
8ca805e1 NI	21
8ca805e1 NI	22	#define CONFIG_BAUDRATE 115200
8ca805e1 NI	23	#define CONFIG_BOOTARGS "console=ttySC3,115200"
8ca805e1 NI	24
18a40e84	25	#define CONFIG_DISPLAY_BOARDINFO
8ca805e1 NI	26	#undef CONFIG_SHOW_BOOT_PROGRESS
	27
	28	/* Ether */
	29	#define CONFIG_SH_ETHER 1
	30	#define CONFIG_SH_ETHER_USE_PORT (0)
	31	#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
	32	#define CONFIG_PHYLIB
	33	#define CONFIG_PHY_SMSC 1
	34	#define CONFIG_BITBANGMII
	35	#define CONFIG_BITBANGMII_MULTI
a80a6619 NI	36	#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
a80a6619 NI	37	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8ca805e1 NI	38	#ifndef CONFIG_SH_ETHER
	39	# define CONFIG_SMC911X
	40	# define CONFIG_SMC911X_16_BIT
	41	# define CONFIG_SMC911X_BASE (0x84000000)
	42	#endif
	43
d7405559	44	/* I2C */
d7405559 NI	45	#define CONFIG_SH_SH7734_I2C 1
	46	#define CONFIG_HARD_I2C 1
	47	#define CONFIG_I2C_MULTI_BUS 1
	48	#define CONFIG_SYS_MAX_I2C_BUS 2
	49	#define CONFIG_SYS_I2C_MODULE 0
	50	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	51	#define CONFIG_SYS_I2C_SLAVE 0x50
	52	#define CONFIG_SH_I2C_DATA_HIGH 4
	53	#define CONFIG_SH_I2C_DATA_LOW 5
	54	#define CONFIG_SH_I2C_CLOCK 500000000
	55	#define CONFIG_SH_I2C_BASE0 0xFFC70000
	56	#define CONFIG_SH_I2C_BASE1 0xFFC7100
	57
8ca805e1 NI	58	/* undef to save memory */
	59	#define CONFIG_SYS_LONGHELP
	60	/* Monitor Command Prompt */
8ca805e1 NI	61	/* Buffer size for input from the Console */
	62	#define CONFIG_SYS_CBSIZE 256
	63	/* Buffer size for Console output */
	64	#define CONFIG_SYS_PBSIZE 256
	65	/* max args accepted for monitor commands */
	66	#define CONFIG_SYS_MAXARGS 16
	67	/* Buffer size for Boot Arguments passed to kernel */
	68	#define CONFIG_SYS_BARGSIZE 512
	69	/* List of legal baudrate settings for this board */
	70	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	71
	72	/* SCIF */
	73	#define CONFIG_SCIF_CONSOLE 1
	74	#define CONFIG_SCIF 1
	75	#define CONFIG_CONS_SCIF3 1
	76
	77	/* Suppress display of console information at boot */
8ca805e1 NI	78
	79	/* SDRAM */
	80	#define CONFIG_SYS_SDRAM_BASE (0x88000000)
	81	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
	82	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
	83
	84	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	85	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
	86	/* Enable alternate, more extensive, memory test */
	87	#undef CONFIG_SYS_ALT_MEMTEST
	88	/* Scratch address used by the alternate memory test */
	89	#undef CONFIG_SYS_MEMTEST_SCRATCH
	90
	91	/* Enable temporary baudrate change while serial download */
	92	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	93
	94	/* FLASH */
	95	#define CONFIG_FLASH_CFI_DRIVER 1
	96	#define CONFIG_SYS_FLASH_CFI
	97	#undef CONFIG_SYS_FLASH_QUIET_TEST
	98	#define CONFIG_SYS_FLASH_EMPTY_INFO
	99	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	100	#define CONFIG_SYS_MAX_FLASH_SECT 512
	101
	102	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
	103	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	104	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	105
	106	/* Timeout for Flash erase operations (in ms) */
	107	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	108	/* Timeout for Flash write operations (in ms) */
	109	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	110	/* Timeout for Flash set sector lock bit operations (in ms) */
	111	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	112	/* Timeout for Flash clear lock bit operations (in ms) */
	113	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	114
	115	/*
	116	* Use hardware flash sectors protection instead
	117	* of U-Boot software protection
	118	*/
	119	#undef CONFIG_SYS_FLASH_PROTECTION
	120	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
	121
	122	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
	123	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	124	/* Monitor size */
	125	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	126	/* Size of DRAM reserved for malloc() use */
	127	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
8ca805e1 NI	128	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	129
	130	/* ENV setting */
	131	#define CONFIG_ENV_IS_IN_FLASH
	132	#define CONFIG_ENV_OVERWRITE 1
	133	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	134	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	135	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	136	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	137	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	138	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	139
	140	/* Board Clock */
	141	#if defined(CONFIG_400MHZ_MODE)
	142	#define CONFIG_SYS_CLK_FREQ 50000000
	143	#else
	144	#define CONFIG_SYS_CLK_FREQ 44444444
	145	#endif
684a501e NI	146	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	147	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8ca805e1	148	#define CONFIG_SYS_TMU_CLK_DIV 4
8ca805e1 NI	149
8ca805e1 NI	150	#endif /* __R0P7734_H */