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Commit | Line | Data |
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f5e2466f NI |
1 | #ifndef __CONFIG_H |
2 | #define __CONFIG_H | |
3 | ||
f5e2466f NI |
4 | #define CONFIG_CPU_SH7751 1 |
5 | #define CONFIG_CPU_SH_TYPE_R 1 | |
6 | #define CONFIG_R2DPLUS 1 | |
7 | #define __LITTLE_ENDIAN__ 1 | |
8 | ||
18a40e84 VZ |
9 | #define CONFIG_DISPLAY_BOARDINFO |
10 | ||
f5e2466f NI |
11 | /* |
12 | * Command line configuration. | |
13 | */ | |
f5e2466f | 14 | #define CONFIG_CMD_PCI |
f5e2466f | 15 | #define CONFIG_CMD_IDE |
f5e2466f | 16 | #define CONFIG_DOS_PARTITION |
c8d47279 | 17 | #define CONFIG_CMD_SH_ZIMAGEBOOT |
f5e2466f NI |
18 | |
19 | /* SCIF */ | |
6c58a030 | 20 | #define CONFIG_SCIF_CONSOLE 1 |
f5e2466f NI |
21 | #define CONFIG_BAUDRATE 115200 |
22 | #define CONFIG_CONS_SCIF1 1 | |
f5e2466f | 23 | |
f5e2466f NI |
24 | #define CONFIG_BOOTARGS "console=ttySC0,115200" |
25 | #define CONFIG_ENV_OVERWRITE 1 | |
26 | ||
f5e2466f | 27 | /* SDRAM */ |
76527047 VZ |
28 | #define CONFIG_SYS_SDRAM_BASE 0x8C000000 |
29 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
6d0f6bcf | 30 | |
47c5705d | 31 | #define CONFIG_SYS_TEXT_BASE 0x8FE00000 |
6d0f6bcf | 32 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
33 | #define CONFIG_SYS_CBSIZE 256 |
34 | #define CONFIG_SYS_PBSIZE 256 | |
35 | #define CONFIG_SYS_MAXARGS 16 | |
36 | #define CONFIG_SYS_BARGSIZE 512 | |
f5e2466f | 37 | |
6d0f6bcf | 38 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 39 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
f5e2466f | 40 | |
6d0f6bcf | 41 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
f5e2466f | 42 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
43 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
44 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
f5e2466f | 45 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 46 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 47 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
f5e2466f NI |
48 | |
49 | /* | |
873d97aa | 50 | * NOR Flash ( Spantion S29GL256P ) |
f5e2466f | 51 | */ |
6d0f6bcf | 52 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 53 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
54 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
55 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
56 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
57 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f5e2466f | 58 | |
5a1aceb0 | 59 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
60 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
61 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf | 62 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
f5e2466f NI |
63 | |
64 | /* | |
65 | * SuperH Clock setting | |
66 | */ | |
67 | #define CONFIG_SYS_CLK_FREQ 60000000 | |
684a501e NI |
68 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
69 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 70 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
6d0f6bcf | 71 | #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ |
f5e2466f NI |
72 | |
73 | /* | |
74 | * IDE support | |
75 | */ | |
76 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_PIO_MODE 1 |
78 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
79 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
80 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
81 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
82 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
83 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
84 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 85 | #define CONFIG_IDE_SWAP_IO |
f5e2466f NI |
86 | |
87 | /* | |
88 | * SuperH PCI Bridge Configration | |
89 | */ | |
f5e2466f NI |
90 | #define CONFIG_SH4_PCI |
91 | #define CONFIG_SH7751_PCI | |
f5e2466f | 92 | #define CONFIG_PCI_SCAN_SHOW 1 |
f5e2466f NI |
93 | #define __mem_pci |
94 | ||
95 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
96 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
97 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
98 | #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ | |
99 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
100 | #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ | |
76527047 VZ |
101 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE |
102 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE | |
2db0e127 | 103 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE |
f5e2466f | 104 | |
f5e2466f | 105 | #endif /* __CONFIG_H */ |