]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/r2dplus.h
Convert CONFIG_ENV_IS_IN_FLASH to Kconfig
[people/ms/u-boot.git] / include / configs / r2dplus.h
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1#ifndef __CONFIG_H
2#define __CONFIG_H
3
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4#define CONFIG_CPU_SH7751 1
5#define CONFIG_CPU_SH_TYPE_R 1
6#define CONFIG_R2DPLUS 1
7#define __LITTLE_ENDIAN__ 1
8
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9#define CONFIG_DISPLAY_BOARDINFO
10
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11/*
12 * Command line configuration.
13 */
f5e2466f 14#define CONFIG_CMD_PCI
c8d47279 15#define CONFIG_CMD_SH_ZIMAGEBOOT
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16
17/* SCIF */
6c58a030 18#define CONFIG_SCIF_CONSOLE 1
f5e2466f 19#define CONFIG_CONS_SCIF1 1
f5e2466f 20
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21#define CONFIG_BOOTARGS "console=ttySC0,115200"
22#define CONFIG_ENV_OVERWRITE 1
23
f5e2466f 24/* SDRAM */
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25#define CONFIG_SYS_SDRAM_BASE 0x8C000000
26#define CONFIG_SYS_SDRAM_SIZE 0x04000000
6d0f6bcf 27
47c5705d 28#define CONFIG_SYS_TEXT_BASE 0x8FE00000
6d0f6bcf 29#define CONFIG_SYS_LONGHELP
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30#define CONFIG_SYS_CBSIZE 256
31#define CONFIG_SYS_PBSIZE 256
32#define CONFIG_SYS_MAXARGS 16
33#define CONFIG_SYS_BARGSIZE 512
f5e2466f 34
6d0f6bcf 35#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a 36#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
f5e2466f 37
6d0f6bcf 38#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
f5e2466f 39/* Address of u-boot image in Flash */
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40#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
41#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
f5e2466f 42/* Size of DRAM reserved for malloc() use */
6d0f6bcf 43#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
6d0f6bcf 44#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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45
46/*
873d97aa 47 * NOR Flash ( Spantion S29GL256P )
f5e2466f 48 */
6d0f6bcf 49#define CONFIG_SYS_FLASH_CFI
00b1883a 50#define CONFIG_FLASH_CFI_DRIVER
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51#define CONFIG_SYS_FLASH_BASE (0xA0000000)
52#define CONFIG_SYS_MAX_FLASH_BANKS (1)
53#define CONFIG_SYS_MAX_FLASH_SECT 256
54#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f5e2466f 55
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56#define CONFIG_ENV_SECT_SIZE 0x40000
57#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf 58#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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59
60/*
61 * SuperH Clock setting
62 */
63#define CONFIG_SYS_CLK_FREQ 60000000
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64#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
65#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632 66#define CONFIG_SYS_TMU_CLK_DIV 4
6d0f6bcf 67#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
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68
69/*
70 * IDE support
71 */
72#define CONFIG_IDE_RESET 1
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73#define CONFIG_SYS_PIO_MODE 1
74#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
75#define CONFIG_SYS_IDE_MAXDEVICE 1
76#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
77#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
78#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
79#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
80#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
f2a37fcd 81#define CONFIG_IDE_SWAP_IO
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82
83/*
84 * SuperH PCI Bridge Configration
85 */
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86#define CONFIG_SH4_PCI
87#define CONFIG_SH7751_PCI
f5e2466f 88#define CONFIG_PCI_SCAN_SHOW 1
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89#define __mem_pci
90
91#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
92#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
93#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
94#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
95#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
96#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
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97#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
98#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
2db0e127 99#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
f5e2466f 100
f5e2466f 101#endif /* __CONFIG_H */