[people/ms/u-boot.git] / include / configs / r2dplus.h

#ifndef __CONFIG_H
#define __CONFIG_H

#undef DEBUG

#define CONFIG_CPU_SH7751	1
#define CONFIG_CPU_SH_TYPE_R	1
#define CONFIG_R2DPLUS		1
#define __LITTLE_ENDIAN__	1

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_SH_ZIMAGEBOOT

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_CONS_SCIF1	1
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(0x04000000)

#define CONFIG_SYS_TEXT_BASE	0x0FFC0000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512

#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/*
 * NOR Flash ( Spantion S29GL256P )
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  256
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

/*
 * SuperH Clock setting
 */
#define CONFIG_SYS_CLK_FREQ	60000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4
#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

/*
 * SuperH PCI Bridge Configration
 */
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW	1
#define __io
#define __mem_pci

#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
#define CONFIG_PCI_SYS_BUS	(CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
#define CONFIG_PCI_SYS_PHYS	(CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
#define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE

#endif /* __CONFIG_H */
Commit	Line	Data
f5e2466f NI	1	#ifndef __CONFIG_H
	2	#define __CONFIG_H
	3
	4	#undef DEBUG
	5
f5e2466f NI	6	#define CONFIG_CPU_SH7751 1
	7	#define CONFIG_CPU_SH_TYPE_R 1
	8	#define CONFIG_R2DPLUS 1
	9	#define __LITTLE_ENDIAN__ 1
	10
	11	/*
	12	* Command line configuration.
	13	*/
f5e2466f	14	#define CONFIG_CMD_PCI
f5e2466f	15	#define CONFIG_CMD_IDE
f5e2466f	16	#define CONFIG_DOS_PARTITION
c8d47279	17	#define CONFIG_CMD_SH_ZIMAGEBOOT
f5e2466f NI	18
f5e2466f NI	19	/* SCIF */
6c58a030	20	#define CONFIG_SCIF_CONSOLE 1
f5e2466f NI	21	#define CONFIG_BAUDRATE 115200
f5e2466f NI	22	#define CONFIG_CONS_SCIF1 1
9660e442	23	#define CONFIG_BOARD_LATE_INIT
f5e2466f	24
f5e2466f NI	25	#define CONFIG_BOOTARGS "console=ttySC0,115200"
	26	#define CONFIG_ENV_OVERWRITE 1
	27
f5e2466f	28	/* SDRAM */
6d0f6bcf JCPV	29	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	30	#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
	31
653f985b	32	#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
6d0f6bcf	33	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	34	#define CONFIG_SYS_CBSIZE 256
	35	#define CONFIG_SYS_PBSIZE 256
	36	#define CONFIG_SYS_MAXARGS 16
	37	#define CONFIG_SYS_BARGSIZE 512
f5e2466f	38
6d0f6bcf	39	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	40	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
f5e2466f	41
6d0f6bcf	42	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
f5e2466f	43	/* Address of u-boot image in Flash */
6d0f6bcf JCPV	44	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	45	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
f5e2466f	46	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	47	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
6d0f6bcf	48	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
f5e2466f NI	49
f5e2466f NI	50	/*
873d97aa	51	* NOR Flash ( Spantion S29GL256P )
f5e2466f	52	*/
6d0f6bcf	53	#define CONFIG_SYS_FLASH_CFI
00b1883a	54	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	55	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	56	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	57	#define CONFIG_SYS_MAX_FLASH_SECT 256
	58	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f5e2466f	59
5a1aceb0	60	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	61	#define CONFIG_ENV_SECT_SIZE 0x40000
0e8d1586 JCPV	62	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	63	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
f5e2466f NI	64
	65	/*
	66	* SuperH Clock setting
	67	*/
	68	#define CONFIG_SYS_CLK_FREQ 60000000
684a501e NI	69	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	70	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	71	#define CONFIG_SYS_TMU_CLK_DIV 4
6d0f6bcf	72	#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
f5e2466f NI	73
	74	/*
	75	* IDE support
	76	*/
	77	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	78	#define CONFIG_SYS_PIO_MODE 1
	79	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	80	#define CONFIG_SYS_IDE_MAXDEVICE 1
	81	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
	82	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	83	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
	84	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
	85	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
f2a37fcd	86	#define CONFIG_IDE_SWAP_IO
f5e2466f NI	87
	88	/*
	89	* SuperH PCI Bridge Configration
	90	*/
	91	#define CONFIG_PCI
	92	#define CONFIG_SH4_PCI
	93	#define CONFIG_SH7751_PCI
	94	#define CONFIG_PCI_PNP
	95	#define CONFIG_PCI_SCAN_SHOW 1
	96	#define __io
	97	#define __mem_pci
	98
	99	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
	100	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	101	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
	102	#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
	103	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	104	#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
2db0e127 YS	105	#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
	106	#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
	107	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
f5e2466f	108
f5e2466f	109	#endif /* __CONFIG_H */