[people/ms/u-boot.git] / include / configs / r7780mp.h

/*
 * Configuation settings for the Renesas R7780MP board
 *
 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __R7780RP_H
#define __R7780RP_H

#define CONFIG_CPU_SH7780	1
#define CONFIG_R7780MP		1
#define CONFIG_SYS_R7780MP_OLD_FLASH	1
#define __LITTLE_ENDIAN__ 1

#define CONFIG_DISPLAY_BOARDINFO

/*
 * Command line configuration.
 */
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION

#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_CONS_SCIF0	1

#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE	1

#define CONFIG_SYS_TEXT_BASE		0x0FFC0000
#define CONFIG_SYS_SDRAM_BASE		(0x08000000)
#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE	512

#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

/* Flash board support */
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
/* NOR Flash (S29PL127J60TFI130) */
# define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
# define CONFIG_SYS_MAX_FLASH_BANKS	(2)
# define CONFIG_SYS_MAX_FLASH_SECT	270
# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
				CONFIG_SYS_FLASH_BASE + 0x100000,\
				CONFIG_SYS_FLASH_BASE + 0x400000,\
				CONFIG_SYS_FLASH_BASE + 0x700000, }
#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
/* NOR Flash (Spantion S29GL256P) */
# define CONFIG_SYS_MAX_FLASH_BANKS	(1)
# define CONFIG_SYS_MAX_FLASH_SECT		256
# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)

#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER	(8)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef  CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4

/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#define CONFIG_SH7780_PCI_LSR	0x07f00001
#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
#define CONFIG_PCI_SCAN_SHOW	1
#define __mem_pci

#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */

#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_BUS  CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* CONFIG_CMD_PCI */

#if defined(CONFIG_CMD_NET)
/* AX88796L Support(NE2000 base chip) */
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE	0xA4100000
#endif

/* Compact flash Support */
#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_RESET        1
#define CONFIG_SYS_PIO_MODE            1
#define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE       1
#define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
#define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
#define CONFIG_IDE_SWAP_IO
#endif /* CONFIG_CMD_IDE */

#endif /* __R7780RP_H */
Commit	Line	Data
c133c1fb YG	1	/*
	2	* Configuation settings for the Renesas R7780MP board
	3	*
ec39d479	4	* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
c133c1fb YG	5	* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
c133c1fb YG	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c133c1fb YG	8	*/
	9
	10	#ifndef __R7780RP_H
	11	#define __R7780RP_H
	12
c133c1fb YG	13	#define CONFIG_CPU_SH7780 1
c133c1fb YG	14	#define CONFIG_R7780MP 1
6d0f6bcf	15	#define CONFIG_SYS_R7780MP_OLD_FLASH 1
ec39d479	16	#define __LITTLE_ENDIAN__ 1
c133c1fb	17
18a40e84 VZ	18	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	19
c133c1fb YG	20	/*
	21	* Command line configuration.
	22	*/
	23	#define CONFIG_CMD_SDRAM
c133c1fb	24	#define CONFIG_CMD_PCI
c133c1fb	25	#define CONFIG_CMD_IDE
c133c1fb YG	26	#define CONFIG_DOS_PARTITION
c133c1fb YG	27
6c58a030	28	#define CONFIG_SCIF_CONSOLE 1
c133c1fb YG	29	#define CONFIG_BAUDRATE 115200
	30	#define CONFIG_CONS_SCIF0 1
	31
c133c1fb YG	32	#define CONFIG_BOOTARGS "console=ttySC0,115200"
	33	#define CONFIG_ENV_OVERWRITE 1
	34
913c8910	35	#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
6d0f6bcf JCPV	36	#define CONFIG_SYS_SDRAM_BASE (0x08000000)
6d0f6bcf JCPV	37	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
c133c1fb	38
6d0f6bcf	39	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	40	#define CONFIG_SYS_CBSIZE 256
	41	#define CONFIG_SYS_PBSIZE 256
	42	#define CONFIG_SYS_MAXARGS 16
	43	#define CONFIG_SYS_BARGSIZE 512
c133c1fb	44
6d0f6bcf	45	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	46	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
c133c1fb	47
ec39d479	48	/* Flash board support */
6d0f6bcf JCPV	49	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
6d0f6bcf JCPV	50	#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
ec39d479	51	/* NOR Flash (S29PL127J60TFI130) */
6d0f6bcf JCPV	52	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
	53	# define CONFIG_SYS_MAX_FLASH_BANKS (2)
	54	# define CONFIG_SYS_MAX_FLASH_SECT 270
	55	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	56	CONFIG_SYS_FLASH_BASE + 0x100000,\
	57	CONFIG_SYS_FLASH_BASE + 0x400000,\
	58	CONFIG_SYS_FLASH_BASE + 0x700000, }
	59	#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
ec39d479	60	/* NOR Flash (Spantion S29GL256P) */
6d0f6bcf JCPV	61	# define CONFIG_SYS_MAX_FLASH_BANKS (1)
	62	# define CONFIG_SYS_MAX_FLASH_SECT 256
	63	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	64	#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
c133c1fb	65
6d0f6bcf	66	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
c133c1fb	67	/* Address of u-boot image in Flash */
6d0f6bcf JCPV	68	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	69	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
c133c1fb	70	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	71	#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
c133c1fb	72
6d0f6bcf JCPV	73	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6d0f6bcf JCPV	74	#define CONFIG_SYS_RX_ETH_BUFFER (8)
c133c1fb	75
6d0f6bcf	76	#define CONFIG_SYS_FLASH_CFI
00b1883a	77	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	78	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
6d0f6bcf JCPV	79	#undef CONFIG_SYS_FLASH_QUIET_TEST
c133c1fb	80	/* print 'E' for empty sector on flinfo */
6d0f6bcf	81	#define CONFIG_SYS_FLASH_EMPTY_INFO
c133c1fb	82
5a1aceb0	83	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	84	#define CONFIG_ENV_SECT_SIZE (256 * 1024)
0e8d1586 JCPV	85	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	86	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	87	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	88	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
c133c1fb YG	89
	90	/* Board Clock */
	91	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	92	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	93	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	94	#define CONFIG_SYS_TMU_CLK_DIV 4
c133c1fb YG	95
	96	/* PCI Controller */
	97	#if defined(CONFIG_CMD_PCI)
c133c1fb	98	#define CONFIG_SH4_PCI
ab8f4d40	99	#define CONFIG_SH7780_PCI
06b18163 YS	100	#define CONFIG_SH7780_PCI_LSR 0x07f00001
	101	#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
	102	#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
c133c1fb	103	#define CONFIG_PCI_SCAN_SHOW 1
c133c1fb YG	104	#define __mem_pci
	105
	106	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
	107	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	108	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
	109
	110	#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
	111	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	112	#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
04366d07 NI	113	#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
	114	#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
	115	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
c133c1fb YG	116	#endif /* CONFIG_CMD_PCI */
	117
	118	#if defined(CONFIG_CMD_NET)
c7c1dbbf	119	/* AX88796L Support(NE2000 base chip) */
c133c1fb YG	120	#define CONFIG_DRIVER_AX88796L
	121	#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
	122	#endif
	123
	124	/* Compact flash Support */
	125	#if defined(CONFIG_CMD_IDE)
	126	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	127	#define CONFIG_SYS_PIO_MODE 1
	128	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	129	#define CONFIG_SYS_IDE_MAXDEVICE 1
	130	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
	131	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	132	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
	133	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
	134	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
f2a37fcd	135	#define CONFIG_IDE_SWAP_IO
c133c1fb YG	136	#endif /* CONFIG_CMD_IDE */
	137
	138	#endif /* __R7780RP_H */