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Commit | Line | Data |
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c133c1fb YG |
1 | /* |
2 | * Configuation settings for the Renesas R7780MP board | |
3 | * | |
ec39d479 | 4 | * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
c133c1fb YG |
5 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c133c1fb YG |
8 | */ |
9 | ||
10 | #ifndef __R7780RP_H | |
11 | #define __R7780RP_H | |
12 | ||
13 | #undef DEBUG | |
c133c1fb YG |
14 | #define CONFIG_CPU_SH7780 1 |
15 | #define CONFIG_R7780MP 1 | |
6d0f6bcf | 16 | #define CONFIG_SYS_R7780MP_OLD_FLASH 1 |
ec39d479 | 17 | #define __LITTLE_ENDIAN__ 1 |
c133c1fb YG |
18 | |
19 | /* | |
20 | * Command line configuration. | |
21 | */ | |
22 | #define CONFIG_CMD_SDRAM | |
c133c1fb | 23 | #define CONFIG_CMD_PCI |
c133c1fb | 24 | #define CONFIG_CMD_IDE |
c133c1fb YG |
25 | #define CONFIG_DOS_PARTITION |
26 | ||
6c58a030 | 27 | #define CONFIG_SCIF_CONSOLE 1 |
c133c1fb YG |
28 | #define CONFIG_BAUDRATE 115200 |
29 | #define CONFIG_CONS_SCIF0 1 | |
30 | ||
c133c1fb YG |
31 | #define CONFIG_BOOTARGS "console=ttySC0,115200" |
32 | #define CONFIG_ENV_OVERWRITE 1 | |
33 | ||
913c8910 | 34 | #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 |
6d0f6bcf JCPV |
35 | #define CONFIG_SYS_SDRAM_BASE (0x08000000) |
36 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) | |
c133c1fb | 37 | |
6d0f6bcf | 38 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
39 | #define CONFIG_SYS_CBSIZE 256 |
40 | #define CONFIG_SYS_PBSIZE 256 | |
41 | #define CONFIG_SYS_MAXARGS 16 | |
42 | #define CONFIG_SYS_BARGSIZE 512 | |
c133c1fb | 43 | |
6d0f6bcf | 44 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 45 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
c133c1fb | 46 | |
ec39d479 | 47 | /* Flash board support */ |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
49 | #ifdef CONFIG_SYS_R7780MP_OLD_FLASH | |
ec39d479 | 50 | /* NOR Flash (S29PL127J60TFI130) */ |
6d0f6bcf JCPV |
51 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
52 | # define CONFIG_SYS_MAX_FLASH_BANKS (2) | |
53 | # define CONFIG_SYS_MAX_FLASH_SECT 270 | |
54 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
55 | CONFIG_SYS_FLASH_BASE + 0x100000,\ | |
56 | CONFIG_SYS_FLASH_BASE + 0x400000,\ | |
57 | CONFIG_SYS_FLASH_BASE + 0x700000, } | |
58 | #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
ec39d479 | 59 | /* NOR Flash (Spantion S29GL256P) */ |
6d0f6bcf JCPV |
60 | # define CONFIG_SYS_MAX_FLASH_BANKS (1) |
61 | # define CONFIG_SYS_MAX_FLASH_SECT 256 | |
62 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
63 | #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
c133c1fb | 64 | |
6d0f6bcf | 65 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
c133c1fb | 66 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
68 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
c133c1fb | 69 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 70 | #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) |
c133c1fb | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
73 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
c133c1fb | 74 | |
6d0f6bcf | 75 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 76 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
77 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
78 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
c133c1fb | 79 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 80 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c133c1fb | 81 | |
5a1aceb0 | 82 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
83 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
84 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
85 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
86 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
87 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
c133c1fb YG |
88 | |
89 | /* Board Clock */ | |
90 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
91 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
92 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 93 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
c133c1fb YG |
94 | |
95 | /* PCI Controller */ | |
96 | #if defined(CONFIG_CMD_PCI) | |
c133c1fb | 97 | #define CONFIG_SH4_PCI |
ab8f4d40 | 98 | #define CONFIG_SH7780_PCI |
06b18163 YS |
99 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
100 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE | |
101 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE | |
c133c1fb YG |
102 | #define CONFIG_PCI_PNP |
103 | #define CONFIG_PCI_SCAN_SHOW 1 | |
104 | #define __io | |
105 | #define __mem_pci | |
106 | ||
107 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
108 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
109 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
110 | ||
111 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ | |
112 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
113 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | |
04366d07 NI |
114 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
115 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
116 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
c133c1fb YG |
117 | #endif /* CONFIG_CMD_PCI */ |
118 | ||
119 | #if defined(CONFIG_CMD_NET) | |
c7c1dbbf | 120 | /* AX88796L Support(NE2000 base chip) */ |
c133c1fb YG |
121 | #define CONFIG_DRIVER_AX88796L |
122 | #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 | |
123 | #endif | |
124 | ||
125 | /* Compact flash Support */ | |
126 | #if defined(CONFIG_CMD_IDE) | |
127 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_PIO_MODE 1 |
129 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
130 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
131 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
132 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
133 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
134 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
135 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 136 | #define CONFIG_IDE_SWAP_IO |
c133c1fb YG |
137 | #endif /* CONFIG_CMD_IDE */ |
138 | ||
139 | #endif /* __R7780RP_H */ |