projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c133c1fb YG |
1 | /* |
| 2 | * Configuation settings for the Renesas R7780MP board | |
| 3 | * | |
| ec39d479 | 4 | * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| c133c1fb YG |
5 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| c133c1fb YG |
8 | */ |
| 9 | ||
| 10 | #ifndef __R7780RP_H | |
| 11 | #define __R7780RP_H | |
| 12 | ||
| c133c1fb YG |
13 | #define CONFIG_CPU_SH7780 1 |
| 14 | #define CONFIG_R7780MP 1 | |
| 6d0f6bcf | 15 | #define CONFIG_SYS_R7780MP_OLD_FLASH 1 |
| ec39d479 | 16 | #define __LITTLE_ENDIAN__ 1 |
| c133c1fb | 17 | |
| 18a40e84 VZ |
18 | #define CONFIG_DISPLAY_BOARDINFO |
| 19 | ||
| c133c1fb YG |
20 | #define CONFIG_CONS_SCIF0 1 |
| 21 | ||
| c133c1fb YG |
22 | #define CONFIG_ENV_OVERWRITE 1 |
| 23 | ||
| 6d0f6bcf JCPV |
24 | #define CONFIG_SYS_SDRAM_BASE (0x08000000) |
| 25 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) | |
| c133c1fb | 26 | |
| 6d0f6bcf | 27 | #define CONFIG_SYS_PBSIZE 256 |
| c133c1fb | 28 | |
| 6d0f6bcf | 29 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
| 14d0a02a | 30 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
| c133c1fb | 31 | |
| ec39d479 | 32 | /* Flash board support */ |
| 6d0f6bcf JCPV |
33 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
| 34 | #ifdef CONFIG_SYS_R7780MP_OLD_FLASH | |
| ec39d479 | 35 | /* NOR Flash (S29PL127J60TFI130) */ |
| 6d0f6bcf JCPV |
36 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
| 37 | # define CONFIG_SYS_MAX_FLASH_BANKS (2) | |
| 38 | # define CONFIG_SYS_MAX_FLASH_SECT 270 | |
| 39 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
| 40 | CONFIG_SYS_FLASH_BASE + 0x100000,\ | |
| 41 | CONFIG_SYS_FLASH_BASE + 0x400000,\ | |
| 42 | CONFIG_SYS_FLASH_BASE + 0x700000, } | |
| 43 | #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
| ec39d479 | 44 | /* NOR Flash (Spantion S29GL256P) */ |
| 6d0f6bcf JCPV |
45 | # define CONFIG_SYS_MAX_FLASH_BANKS (1) |
| 46 | # define CONFIG_SYS_MAX_FLASH_SECT 256 | |
| 47 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 48 | #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
| c133c1fb | 49 | |
| 6d0f6bcf | 50 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
| c133c1fb | 51 | /* Address of u-boot image in Flash */ |
| 6d0f6bcf JCPV |
52 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
| 53 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
| c133c1fb | 54 | /* Size of DRAM reserved for malloc() use */ |
| 6d0f6bcf | 55 | #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) |
| c133c1fb | 56 | |
| 6d0f6bcf JCPV |
57 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 58 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
| c133c1fb | 59 | |
| 6d0f6bcf | 60 | #define CONFIG_SYS_FLASH_CFI |
| 00b1883a | 61 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
62 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
| 63 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
| c133c1fb | 64 | /* print 'E' for empty sector on flinfo */ |
| 6d0f6bcf | 65 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| c133c1fb | 66 | |
| 0e8d1586 JCPV |
67 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
| 68 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
| 6d0f6bcf JCPV |
69 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 70 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
| 71 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
| c133c1fb YG |
72 | |
| 73 | /* Board Clock */ | |
| 74 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
| 684a501e NI |
75 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
| 76 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
| be45c632 | 77 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
| c133c1fb YG |
78 | |
| 79 | /* PCI Controller */ | |
| 80 | #if defined(CONFIG_CMD_PCI) | |
| c133c1fb | 81 | #define CONFIG_SH4_PCI |
| ab8f4d40 | 82 | #define CONFIG_SH7780_PCI |
| 06b18163 YS |
83 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
| 84 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE | |
| 85 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE | |
| c133c1fb | 86 | #define CONFIG_PCI_SCAN_SHOW 1 |
| c133c1fb YG |
87 | #define __mem_pci |
| 88 | ||
| 89 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
| 90 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
| 91 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
| 92 | ||
| 93 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ | |
| 94 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
| 95 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | |
| 04366d07 NI |
96 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
| 97 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
| 98 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
| c133c1fb YG |
99 | #endif /* CONFIG_CMD_PCI */ |
| 100 | ||
| 101 | #if defined(CONFIG_CMD_NET) | |
| c7c1dbbf | 102 | /* AX88796L Support(NE2000 base chip) */ |
| c133c1fb YG |
103 | #define CONFIG_DRIVER_AX88796L |
| 104 | #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 | |
| 105 | #endif | |
| 106 | ||
| 107 | /* Compact flash Support */ | |
| fc843a02 | 108 | #if defined(CONFIG_IDE) |
| c133c1fb | 109 | #define CONFIG_IDE_RESET 1 |
| 6d0f6bcf JCPV |
110 | #define CONFIG_SYS_PIO_MODE 1 |
| 111 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
| 112 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
| 113 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
| 114 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
| 115 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
| 116 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
| 117 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
| f2a37fcd | 118 | #define CONFIG_IDE_SWAP_IO |
| fc843a02 | 119 | #endif /* CONFIG_IDE */ |
| c133c1fb YG |
120 | |
| 121 | #endif /* __R7780RP_H */ |